Inventor

CERNEA RAUL-ADRIAN

US159 patents

⚠️ This page may combine multiple inventors who share the name “CERNEA RAUL-ADRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CERNEA RAUL-ADRIAN

SANDISK CORP

Time-dependent compensation currents in non-volatile memory read operations

Non-volatile memory and method with reduced source line bias errors

Compensating for coupling in non-volatile storage

Compensation currents in non-volatile memory read operations

Flexible and area efficient column redundancy for non-volatile memories

Use of data latches in multi-phase programming of non-volatile memories

Memory sensing circuit and method for low voltage operation

Non-volatile memory and method with improved sensing

Non-volatile memory and method with reduced neighboring field errors

Highly compact non-volatile memory and method thereof

Non-volatile memory and method with bit line compensation dependent on neighboring operating modes

Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells

Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells

Operating techniques for reducing program and read disturbs of a non-volatile memory

Non-volatile memory with temperature-compensated data read

Segmented metal bitlines

Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM

Programmable power generation circuit for flash EEPROM memory systems

Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range

Programmable power generation circuit for flash EEPROM memory systems

Programmable power generation circuit for flash eeprom memory systems

Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells

Programmable power generation circuit for flash EEPROM memory systems

Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells

Non-volatile storage system with resistance sensing and compensation

Resistance sensing and compensation for non-volatile storage

Method for compensated sensing in non-volatile memory

Compensating for coupling in non-volatile storage

Latched programming of memory and method

Non-volatile memory and method with compensation for source line bias errors

Charge pump with fibonacci number multiplication

Non-volatile memory and method with bit line coupled compensation

Operating techniques for reducing program and read disturbs of a non-volatile memory

Area efficient charge pump

Highly compact non-volatile memory and method therefor with internal serial buses

Background operation for memory cells

Latched address multi-chunk write to EEPROM

Memory array architecture utilizing global bit lines shared by multiple cells

Non-volatile memory with improved sensing and method therefor

Programmable power generation circuit for flash EEPROM memory systems

Non-volatile memory and method with bit line to bit line coupled compensation

Non-volatile memory with redundancy data buffered in remote buffer circuits

Non-volatile memory and method with bit line compensation dependent on neighboring operating modes

Non-volatile memory and method with control gate compensation for source line bias errors

Area efficient charge pump

Memory device with pointer structure to map logical to physical addresses

Dynamic column block selection

Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM

SUNDISK CORP

Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells

Charge pump circuit with exponetral multiplication