Inventor

KAPUR MOHIT

US25 patents

⚠️ This page may combine multiple inventors who share the name “KAPUR MOHIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAPUR MOHIT

IBM

Secure processing environment for protecting sensitive information

Phase continuous signal generation using direct digital synthesis

Error type identification circuit for identifying different types of errors in communications devices

Clock scaling circuit

Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Secure processing environment for protecting sensitive information

System and method for supporting secure objects using a memory access control monitor

Secure processing environment for protecting sensitive information

Non-blocking hardware function request retries to address response latency variabilities

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Self-synchronizing pseudorandom bit sequence checker

Self-synchronizing pseudorandom bit sequence checker

Transmit and receive radio frequency (RF) signals without the use of baseband generators and local oscillators for up conversion and down conversion

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Testable digital delay line

Minimizing hash collisions of composite keys

Secure processing environment for protecting sensitive information

System and method for supporting secure objects using a memory access control monitor

Secure processing environment for protecting sensitive information

ASAAD SAMEH

Wire like link for cycle reproducible and cycle accurate hardware accelerator

Increasing throughput of multiplexed electrical bus in pipe-lined architecture

ASAAD SAMEH W

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

ASAAD SAMETH W

Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator