Inventor

LI YISUO

SG22 patents

⚠️ This page may combine multiple inventors who share the name “LI YISUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI YISUO

CHARTERED SEMICONDUCTOR MFG

LDMOS using a combination of enhanced dielectric stress layer and dummy gates

Semiconductor device layout and channeling implant process

Semiconductor device layout and channeling implant process

Semiconductor device layout and channeling implant process

Semiconductor structure including high voltage device

Shallow low energy ion implantation into pad oxide for improving threshold voltage stability

Structure and method to form source and drain regions over doped depletion regions

UNISANTIS ELECT SINGAPORE PTE

Pillar-shaped semiconductor device and manufacturing method thereof

Method for manufacturing three-dimensional semiconductor device

Surround gate CMOS semiconductor device

Semiconductor device production method and semiconductor device

Semiconductor device production method and semiconductor device

CHU SANFORD

High performance LDMOS device having enhanced dielectric strain layer

LDMOS using a combination of enhanced dielectric stress layer and dummy gates

High performance LDMOS device having enhanced dielectric strain layer

MASUOKA FUJIO

Surrounding gate transistor (SGT) structure

Surround gate CMOS semiconductor device

GLOBALFOUNDRIES SG PTE LTD

Integrated circuit system employing an elevated drain

Structure and method to form source and drain regions over doped depletion regions

CHARTERED SEMICONDUCTOR MFG L

Low cost source drain elevation through poly amorphizing implant technology

KOO JEOUNG MO

Semiconductor structure including high voltage device

LI YISUO

Integrated circuit system with double doped drain transistor