Inventor
KUNDU ARUNANGSHU
US31 patents
⚠️ This page may combine multiple inventors who share the name “KUNDU ARUNANGSHU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ACTEL CORP
29 patentsUS6838902B1Jan 4, 2005
Synchronous first-in/first-out block memory for a field programmable gate array
ACTEL CORP196 citations98
US6751723B1Jun 15, 2004
Field programmable gate array and microcontroller system-on-a-chip
ACTEL CORP107 citations97
US6980028B1Dec 27, 2005
Dedicated input/output first in/first out module for a field programmable gate array
ACTEL CORP13 citations93
US6867615B1Mar 15, 2005
Dedicated input/output first in/first out module for a field programmable gate array
ACTEL CORP28 citations93
US6980027B2Dec 27, 2005
Synchronous first-in/first-out block memory for a field programmable gate array
ACTEL CORP12 citations92
US6825690B1Nov 30, 2004
Clock tree network in a field programmable gate array
ACTEL CORP29 citations92
US7069419B2Jun 27, 2006
Field programmable gate array and microcontroller system-on-a-chip
ACTEL CORP14 citations91
US7375553B1May 20, 2008
Clock tree network in a field programmable gate array
ACTEL CORP12 citations84
US7102385B2Sep 5, 2006
Dedicated input/output first in/first out module for a field programmable gate array
ACTEL CORP11 citations84
US7049846B1May 23, 2006
Clock tree network in a field programmable gate array
ACTEL CORP12 citations84
US7516303B2Apr 7, 2009
Field programmable gate array and microcontroller system-on-a-chip
ACTEL CORP11 citations82
US7484113B1Jan 27, 2009
Delay locked loop for an FPGA architecture
ACTEL CORP8 citations82
US6750674B1Jun 15, 2004
Carry chain for use between logic modules in a field programmable gate array
ACTEL CORP16 citations77
US7385419B1Jun 10, 2008
Dedicated input/output first in/first out module for a field programmable gate array
ACTEL CORP7 citations74
US7199609B1Apr 3, 2007
Dedicated input/output first in/first out module for a field programmable gate array
ACTEL CORP8 citations74
US7394289B2Jul 1, 2008
Synchronous first-in/first-out block memory for a field programmable gate array
ACTEL CORP4 citations73
US7385420B1Jun 10, 2008
Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
ACTEL CORP6 citations73
US7227380B2Jun 5, 2007
Synchronous first-in/first-out block memory for a field programmable gate array
ACTEL CORP6 citations73
US6891396B1May 10, 2005
Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
ACTEL CORP6 citations73
US7171575B1Jan 30, 2007
Delay locked loop for and FPGA architecture
ACTEL CORP9 citations72
US6976185B1Dec 13, 2005
Delay locked loop for an FPGA architecture
ACTEL CORP10 citations72
US7545168B2Jun 9, 2009
Clock tree network in a field programmable gate array
ACTEL CORP5 citations63
US6946871B1Sep 20, 2005
Multi-level routing architecture in a field programmable gate array having transmitters and receivers
ACTEL CORP4 citations63
US7075334B1Jul 11, 2006
Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
ACTEL CORP3 citations62
US7886130B2Feb 8, 2011
Field programmable gate array and microcontroller system-on-a-chip
ACTEL CORP2 citations61
US7432733B1Oct 7, 2008
Multi-level routing architecture in a field programmable gate array having transmitters and receivers
ACTEL CORP0 citations52
US7126374B2Oct 24, 2006
Multi-level routing architecture in a field programmable gate array having transmitters and receivers
ACTEL CORP1 citations52
US7941685B2May 10, 2011
Delay locked loop for an FPGA architecture
ACTEL CORP0 citations51
US7579869B2Aug 25, 2009
Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
ACTEL CORP0 citations51