Inventor

KANUMA AKIRA

JP19 patents

⚠️ This page may combine multiple inventors who share the name “KANUMA AKIRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KANUMA AKIRA

TOSHIBA KK

Data output circuit with means for preventing more than half the output lines from transitioning simultaneously

Single chip microcomputer having a dedicated address bus and dedicated data bus for transferring register bank data to and from an on-line RAM

High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank

Apparatus for selectively accessing different memory types by storing memory correlation information in preprocessing mode and using the information in processing mode

Logic integrated circuit capable of simplifying a test

Integrated circuit with divided power supply wiring

Address multiplexing apparatus

Logic circuit including input and output registers with data bypass and computation circuit with data pass

Logic circuit having normal input/output data paths disabled when test data is transferred during macrocell testing

Semiconductor integrated circuit device

Logic circuit

High speed data communication control device having an uncompetitive bus construction

Communication control device having an apparatus for detecting the absence of a control data on a ring communication network

TOKYO SHIBAURA ELECTRIC CO

Substrate bias generation circuit

Priority determination circuit

Arithmetic operation circuit

Floating-point arithmetic operation system

Method and system for processing exponents in floating-point multiplication

FUJITSU LTD

Test pattern generating apparatus, circuit designing apparatus, test pattern generating method, circuit designing method, test pattern generating program and circuit designing program