P

Inventor

KYNETT VIRGIL N

US16 patents

Patents

16 patents
US5355464AOct 11, 1994

Circuitry and method for suspending the automated erasure of a non-volatile semiconductor memory

INTEL CORP136 citations98
US5341330AAug 23, 1994

Method for writing to a flash memory array during erase suspend intervals

INTEL CORP206 citations98
US5222046AJun 22, 1993

Processor controlled command port architecture for flash memory

INTEL CORP167 citations98
US5053990AOct 1, 1991

Program/erase selection for flash memory

INTEL CORP354 citations98
US5513333AApr 30, 1996

Circuitry and method for programming and erasing a non-volatile semiconductor memory

INTEL CORP42 citations96
US5448712ASep 5, 1995

Circuitry and method for programming and erasing a non-volatile semiconductor memory

INTEL CORP53 citations96
US5377145ADec 27, 1994

Circuitry and method for programming and erasing a non-volatile semiconductor memory

INTEL CORP61 citations96
US5197034AMar 23, 1993

Floating gate non-volatile memory with deep power down and write lock-out

INTEL CORP62 citations95
US5224070AJun 29, 1993

Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

INTEL CORP101 citations94
US5603036AFeb 11, 1997

Power management system for components used in battery powered applications

INTEL CORP37 citations92
US5546561AAug 13, 1996

Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-volatile semiconductor memory

INTEL CORP45 citations92
US5249158ASep 28, 1993

Flash memory blocking architecture

INTEL CORP60 citations92
US5513136AApr 30, 1996

Nonvolatile memory with blocks and circuitry for selectively protecting the blocks for memory operations

INTEL CORP50 citations91
US5463757AOct 31, 1995

Command interface between user commands and a memory device

INTEL CORP43 citations88
US5850509ADec 15, 1998

Circuitry for propagating test mode signals associated with a memory array

INTEL CORP8 citations74
US5339320AAug 16, 1994

Architecture of circuitry for generating test mode signals

INTEL CORP15 citations74