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Inventor
TANIYOSHI ITSUROU
JP
2 patents
Patents
2 patents
US5604775A
Feb 18, 1997
Digital phase locked loop having coarse and fine stepsize variable delay lines
NEC CORP
197 citations
95
US6351756B1
Feb 26, 2002
Clock signal multiplier circuit for a clock signal generator circuit
NEC CORP
32 citations
87