Inventor
HARGROVE MICHAEL J
US30 patents
⚠️ This page may combine multiple inventors who share the name “HARGROVE MICHAEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS6531375B1Mar 11, 2003
Method of forming a body contact using BOX modification
IBM78 citations96
US6320225B1Nov 20, 2001
SOI CMOS body contact through gate, self-aligned to source- drain diffusions
IBM74 citations96
US6372559B1Apr 16, 2002
Method for self-aligned vertical double-gate MOSFET
IBM121 citations94
US6531741B1Mar 11, 2003
Dual buried oxide film SOI structure and method of manufacturing the same
IBM34 citations93
US6433587B1Aug 13, 2002
SOI CMOS dynamic circuits having threshold voltage control
IBM44 citations93
US6344671B1Feb 5, 2002
Pair of FETs including a shared SOI body contact and the method of forming the FETs
IBM19 citations93
US6756637B2Jun 29, 2004
Method of controlling floating body effects in an asymmetrical SOI device
IBM22 citations90
US6613615B2Sep 2, 2003
Pair of FETs including a shared SOI body contact and the method of forming the FETs
IBM7 citations74
US6426244B2Jul 30, 2002
Process of forming a thick oxide field effect transistor
IBM7 citations74
US6323522B1Nov 27, 2001
Silicon on insulator thick oxide structure and process of manufacture
IBM9 citations74
US6369434B1Apr 9, 2002
Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors
IBM2 citations62
GLOBALFOUNDRIES INC
7 patentsUS8361894B1Jan 29, 2013
Methods of forming FinFET semiconductor devices with different fin heights
GLOBALFOUNDRIES INC34 citations91
US8039349B2Oct 18, 2011
Methods for fabricating non-planar semiconductor devices having stress memory
GLOBALFOUNDRIES INC9 citations84
US7977174B2Jul 12, 2011
FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same
GLOBALFOUNDRIES INC11 citations84
US7939852B2May 10, 2011
Transistor device having asymmetric embedded strain elements and related manufacturing method
GLOBALFOUNDRIES INC10 citations84
US9437740B2Sep 6, 2016
Epitaxially forming a set of fins in a semiconductor device
GLOBALFOUNDRIES INC2 citations61
US9530864B2Dec 27, 2016
Junction overlap control in a semiconductor device using a sacrificial spacer layer
GLOBALFOUNDRIES INC1 citations51
US9034737B2May 19, 2015
Epitaxially forming a set of fins in a semiconductor device
GLOBALFOUNDRIES INC1 citations51
ADVANCED MICRO DEVICES INC
5 patentsUS7767534B2Aug 3, 2010
Methods for fabricating MOS devices having highly stressed channels
ADVANCED MICRO DEVICES INC16 citations92
US7723192B2May 25, 2010
Integrated circuit long and short channel metal gate devices and method of manufacture
ADVANCED MICRO DEVICES INC16 citations92
US7998832B2Aug 16, 2011
Semiconductor device with isolation trench liner, and related fabrication methods
ADVANCED MICRO DEVICES INC11 citations84
US7994014B2Aug 9, 2011
Semiconductor devices having faceted silicide contacts, and related fabrication methods
ADVANCED MICRO DEVICES INC11 citations84
US7902599B2Mar 8, 2011
Integrated circuit having long and short channel metal gate devices and method of manufacture
ADVANCED MICRO DEVICES INC8 citations84