Inventor
MAYFIELD MICHAEL JOHN
US23 patents
Patents
23 patentsUS5737565AApr 7, 1998
System and method for diallocating stream from a stream buffer
IBM104 citations98
US6895482B1May 17, 2005
Reordering and flushing commands in a computer memory subsystem
IBM79 citations97
US6574712B1Jun 3, 2003
Software prefetch system and method for predetermining amount of streamed data
IBM130 citations97
US6446167B1Sep 3, 2002
Cache prefetching of L2 and L3
IBM79 citations97
US6460115B1Oct 1, 2002
System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism
IBM109 citations96
US6085291AJul 4, 2000
System and method for selectively controlling fetching and prefetching of data to a processor
IBM67 citations95
US5758119AMay 26, 1998
System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache
IBM55 citations95
US5740399AApr 14, 1998
Modified L1/L2 cache inclusion for aggressive prefetch
IBM63 citations95
US6968431B2Nov 22, 2005
Method and apparatus for livelock prevention in a multiprocessor system
IBM22 citations92
US6915415B2Jul 5, 2005
Method and apparatus for mapping software prefetch instructions to hardware prefetch logic
IBM37 citations92
US6535962B1Mar 18, 2003
System and method for prefetching data using a hardware prefetch mechanism
IBM48 citations92
US6446170B1Sep 3, 2002
Efficient store machine in cache based microprocessor
IBM20 citations92
US6202128B1Mar 13, 2001
Method and system for pre-fetch cache interrogation using snoop port
IBM24 citations92
US5809529ASep 15, 1998
Prefetching of committed instructions from a memory to an instruction cache
IBM23 citations92
US5787478AJul 28, 1998
Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy
IBM43 citations92
US5664147ASep 2, 1997
System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated
IBM42 citations92
US6578130B2Jun 10, 2003
Programmable data prefetch pacing
IBM35 citations91
US5721864AFeb 24, 1998
Prefetching instructions between caches
IBM37 citations90
US7305526B2Dec 4, 2007
Method, system, and program for transferring data directed to virtual memory addresses to a device memory
IBM13 citations84
US5860150AJan 12, 1999
Instruction pre-fetching of a cache line within a processor
IBM17 citations81
US6587930B1Jul 1, 2003
Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock
IBM8 citations72
US6298417B1Oct 2, 2001
Pipelined cache memory deallocation and storeback
IBM3 citations62
US7171445B2Jan 30, 2007
Fixed snoop response time for source-clocked multiprocessor busses
IBM0 citations39