Inventor
SINGH RAJINDER PAUL
US11 patents
⚠️ This page may combine multiple inventors who share the name “SINGH RAJINDER PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
10 patentsUS5787478AJul 28, 1998
Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy
IBM43 citations92
US5699288ADec 16, 1997
Compare circuit for content-addressable memories
IBM59 citations92
US6240487B1May 29, 2001
Integrated cache buffers
IBM22 citations90
US5937429AAug 10, 1999
Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator
IBM20 citations90
US5802567ASep 1, 1998
Mechanism for managing offset and aliasing conditions within a content-addressable memory-based cache memory
IBM30 citations90
US5761714AJun 2, 1998
Single-cycle multi-accessible interleaved cache
IBM18 citations83
US5905999AMay 18, 1999
Cache sub-array arbitration
IBM13 citations72
US6041390AMar 21, 2000
Token mechanism for cache-line replacement within a cache memory having redundant cache lines
IBM9 citations71
US6304939B1Oct 16, 2001
Token mechanism for cache-line replacement within a cache memory having redundant cache lines
IBM3 citations60
US6064245AMay 16, 2000
Dynamic circuit for capturing data with wide reset tolerance
IBM2 citations60