Inventor

KAHLE JAMES ALLAN

US88 patents

⚠️ This page may combine multiple inventors who share the name “KAHLE JAMES ALLAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAHLE JAMES ALLAN

IBM

Method and apparatus for patching problematic instructions in a microprocessor using software interrupts

System and method for sharing memory by heterogeneous processors

Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism

Partitioned issue queue and allocation strategy

Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization

Method and system for controlled distribution of application code and content data within a computer network

Method and system for controlled distribution of application code and content data within a computer network

Processor with redundant logic

Software prefetch system and method for predetermining amount of streamed data

System and method for tracing

Method and system for simultaneous variable-width bus access in a multiprocessor system

Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access

On-chip data transfer in multi-processor system

Microprocessor with primary and secondary issue queue

Recovery from hang condition in a microprocessor

System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism

Indirect unconditional branches in data processing system emulation mode

Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access

DMA prefetch

Basic block cache microprocessor with instruction history information

Secondary reorder buffer microprocessor

Method and system for interrupt handling during emulation in a data processing system

Method and system for processing branch instructions during emulation in a data processing system

Method and system for emulating instructions by performing an operation directly using special-purpose register contents

System and method for maintaining coherency of information transferred between multiple devices

Computer architecture and software cells for broadband networks

Memory management for real-time applications

Method and apparatus for coherent memory structure of heterogeneous processor systems

Memory management in multiprocessor system

Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions

Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value

Shared execution unit in a dual core processor

Processor and method for separately predicting conditional branches dependent on lock acquisition

Method and system for software control of hardware branch prediction mechanism in a data processor

Converting short branches to predicated instructions

Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling

Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing

Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors

Method and system for performing an emulation context save and restore that is transparent to the operating system

Method and system for minimizing the number of cycles required to execute semantic routines

Method and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside buffer

Method and system for increased instruction dispatch efficiency in a superscalar processor system

System and method for sharing memory by heterogeneous processors

Cacheable DMA

Circuits and methods for recovering link stack data upon branch instruction mis-speculation

Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor

Method and system for performing atomic memory accesses in a processor system

SONY COMPUTER ENTERTAINMENT INC

Methods and apparatus for supporting multiple configurations in a multi-processor system

Methods and apparatus for supporting multiple configurations in a multi-processor system

INTERNATIIONAL BUSINESS MACHIN

Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits