Inventor

HE JIANGQI

US55 patents

⚠️ This page may combine multiple inventors who share the name “HE JIANGQI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HE JIANGQI

INTEL CORP

Integrated micro-channels for 3D through silicon architectures

Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same

Electronic assembly with stacked IC&#39;s using two or more different connection technologies and methods of manufacture

Chip-to-chip optical interconnect

Reducing parasitic mutual capacitances

Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same

Reference slots for signal traces

Extended thin film capacitor (TFC)

Vertical capacitor apparatus, systems, and methods

Electronic assembly

Package level integration of antenna and RF front-end module

Integrated circuit package with chip-side signal connections

Data signal interconnection with reduced crosstalk

IC package with signal land pads

Dual die package with high-speed interconnect

Circuit board with trace configuration for high-speed digital differential signaling

Transmission line impedance matching

Extended thin film capacitor (TFC)

Circuit board with trace configuration for high-speed digital differential signaling

Low impedance inter-digital capacitor and method of using

Multi-chip assembly with optically coupled die

Shielding a connector to reduce interference

Forming compliant contact pads for semiconductor packages

Integrated circuit package with chip-side signal connections

I/O Architecture for integrated circuit package

Transmission line impedance matching

Vertical capacitor apparatus, systems, and methods

Array capacitor apparatuses to filter input/output signal

Transmission line impedance matching

Low impedance inter-digital capacitor and method of using

Circuit board with trace configuration for high-speed digital differential signaling

Low parasitic inductance capacitor with central terminals

Low impedance, high-power socket and method of using

Multi-chip assembly with optically coupled die

Silicon building block architecture with flex tape

Power/ground configuration for low impedance integrated circuit

Package level noise isolation

Silicon building blocks in integrated circuit packaging

Silicon building blocks in integrated circuit packaging

Integrated circuit package to provide high-bandwidth communication among multiple dice

Reducing input capacitance of high speed integrated circuits

Integrated inductors and compliant interconnects for semiconductor packaging

Substrate with raised edge pads

Forming compliant contact pads for semiconductor packages

Multilayer inductor with shielding plane

Packaged spiral inductor structures, processes of making same, and systems containing same

HUAWEI TECH CO LTD

Embedded thin-film magnetic inductor design for integrated voltage regulator (IVR) applications

Chip-process-variation-aware power-efficiency optimization

ZHOU QING A

Multi-chip assembly with optically coupled die

ZHOU QING

Forming compliant contact pads for semiconductor packages

Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture