Inventor

LAU VICTOR

US22 patents

⚠️ This page may combine multiple inventors who share the name “LAU VICTOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAU VICTOR

INTEL CORP

Wide-port context cache apparatus, systems, and methods

DMA completion processing mechanism

Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications

Hardware oriented target-side native command queuing tag management

Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support

Staggered spin-up disable mechanism

DMA descriptor management mechanism

Universal timeout mechanism

Dynamic memory buffer allocation method and system

Hardware oriented host-side native command queuing tag management

Data buffer management in a resource limited environment

Frame order processing apparatus, systems, and methods

Method using port task scheduler

Serial ATA port addressing

Task context direct indexing in a protocol engine

System and method for dynamic data prefetching

Command scheduling and affiliation management for serial attached storage devices

Mechanism to handle uncorrectable write data errors

LAU VICTOR

Multi-threaded transmit transport engine for storage devices

CHANG NAICHIH

Task scheduling to devices with same connection address

INTER CORP

Parallel processing of frame based data transfers

VALERIO HECTOR A

Modular system and method for simulating performance of an electrical device