Inventor

RAMACHANDRAN VIDHYA

US52 patents

⚠️ This page may combine multiple inventors who share the name “RAMACHANDRAN VIDHYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMACHANDRAN VIDHYA

IBM

Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same

Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same

FEOL/MEOL metal resistor for high end CMOS

Trench metal-insulator-metal (MIM) capacitors and method of fabricating same

Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme

Metal-insulator-metal capacitor and method of fabrication

Semiconductor integrated circuit devices having high-Q wafer back-side capacitors

Semiconductor integrated circuit devices having high-Q wafer back-side capacitors

Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same

Trench metal-insulator metal (MIM) capacitors

Structure and method for integrating MIM capacitor in BEOL wiring levels

Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask

Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits

Bipolar and CMOS integration with reduced contact height

Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme

Self-aligned contact

Non-Continuous encapsulation layer for MIM capacitor

Non-continuous encapsulation layer for MIM capacitor

Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices

Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask

APPLE INC

Structure and method for fabricating a computing system with an integrated voltage regulator module

Power management system switched capacitor voltage regulator with integrated passive device

Integrated circuit die decoupling system with reduced inductance

Wafer reconstitution and die-stitching

Wafer reconstitution and die-stitching

Trimmable banked capacitor

Structure and method for fabricating a computing system with an integrated voltage regulator module

Dual-sided silicon integrated passive devices

Power management system switched capacitor voltage regulator with integrated passive device

Structure and method for fabricating a computing system with an integrated voltage regulator module

Wafer reconstitution and die-stitching

Structure and method for fabricating a computing system with an integrated voltage regulator module

Power management system switched capacitor voltage regulator with integrated passive device

Structure and method for fabricating a computing system with an integrated voltage regulator module

Structure and method for sealing a silicon IC

Structure and method for sealing a silicon IC

Dual-sided silicon integrated passive devices

Integrated passive devices to reduce power supply voltage droop

QUALCOMM INC

Integrating through substrate vias from wafer backside layers of integrated circuits

Interposer integrated with 3D passive devices

Integrating through substrate vias into middle-of-line layers of integrated circuits

Small form factor magnetic shield for magnetorestrictive random access memory (MRAM)

Electrically reconfigurable interposer with built-in resistive memory

Electrostatic discharge diodes and methods of forming electrostatic discharge diodes

Method for strain-relieved through substrate vias

Small form factor magnetic shield for magnetorestrictive random access memory (MRAM)

Electrostatic discharge diode

Interposer having stacked devices

RAMACHANDRAN VIDHYA

Structure and method for strain-relieved TSV

Low-K dielectric protection spacer for patterning through substrate vias through a low-K wiring layer