Inventor

SCHEUERLEIN ROY E

US227 patents

⚠️ This page may combine multiple inventors who share the name “SCHEUERLEIN ROY E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHEUERLEIN ROY E

SANDISK 3D LLC

Structure and method for biasing phase change memory array for reliable writing

Switchable resistive memory with opposite polarity write pulses

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

Three-dimensional memory device incorporating segmented bit line memory array

Memory array incorporating memory cells arranged in NAND strings

Integrated circuit including memory array incorporating multiple types of NAND string structures

Word line arrangement having multi-layer word line segments for three-dimensional memory array

Reverse set with current limit for non-volatile storage

Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse

Cross point memory cell with distributed diodes and method of making same

Method to program a memory cell comprising a carbon nanotube fabric and a steering element

Methods and apparatus for extending the effective thermal operating range of a memory

Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics

Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

High bandwidth one time field-programmable memory

High density contact to relaxed geometry layers

Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders

Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements

Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements

Pipeline circuit for low latency memory

Memory device and method for redundancy/self-repair

Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics

Method and apparatus for incorporating block redundancy in a memory array

MATRIX SEMICONDUCTOR INC

NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same

Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor

Method for fabricating programmable memory array structures incorporating series-connected transistor strings

Word line arrangement having multi-layer word line segments for three-dimensional memory array

Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device

Apparatus and method for disturb-free programming of passive element memory cells

Method for programming a three-dimensional memory array incorporating serial chain diode stack

Three-dimensional memory array incorporating serial chain diode stack

Method and apparatus for biasing selected and unselected array lines when writing a memory array

Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays

Transistor layout configuration for tight-pitched memory array lines

Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells

Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions

Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch

Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor

Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays

Memory device and method for temperature-based control over write and/or read operations

Memory device and method for sensing while programming a non-volatile memory cell

Method and apparatus for writing memory arrays using external source of high programming voltage

Memory array incorporating noise detection line

Method and system for increasing programming bandwidth in a non-volatile memory device

Method and apparatus for discharging memory array lines

Integrated systems using vertically-stacked three-dimensional memory cells

SANDISK CORP

Structure and method for biasing phase change memory array for reliable writing

Volatile memory cell two-pass writing method

SCHEUERLEIN ROY E

Structure and method for biasing phase change memory array for reliable writing

IBM

Formation of arrays of microelectronic elements