Inventor
PERISETTY SRINIVAS
US33 patents
⚠️ This page may combine multiple inventors who share the name “PERISETTY SRINIVAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
23 patentsUS7675317B2Mar 9, 2010
Integrated circuits with adjustable body bias and power supply circuitry
ALTERA CORP128 citations98
US7920410B1Apr 5, 2011
Memory elements with increased write margin and soft error upset immunity
ALTERA CORP43 citations96
US7639041B1Dec 29, 2009
Hotsocket-compatible body bias circuitry with power-up current reduction capabilities
ALTERA CORP21 citations92
US7639067B1Dec 29, 2009
Integrated circuit voltage regulator
ALTERA CORP45 citations92
US7571413B1Aug 4, 2009
Testing circuitry for programmable logic devices with selectable power supply voltages
ALTERA CORP21 citations92
US7405589B2Jul 29, 2008
Apparatus and methods for power management in integrated circuits
ALTERA CORP13 citations92
US7355437B2Apr 8, 2008
Latch-up prevention circuitry for integrated circuits with transistor body biasing
ALTERA CORP29 citations92
US7330049B2Feb 12, 2008
Adjustable transistor body bias generation circuitry with latch-up prevention
ALTERA CORP24 citations92
US8369175B1Feb 5, 2013
Memory elements with voltage overstress protection
ALTERA CORP7 citations84
US7990664B1Aug 2, 2011
Electrostatic discharge protection in a field programmable gate array
ALTERA CORP7 citations84
US7978450B1Jul 12, 2011
Electrostatic discharge protection circuitry
ALTERA CORP10 citations84
US7863968B1Jan 4, 2011
Variable-output current-load-independent negative-voltage regulator
ALTERA CORP10 citations84
US7592832B2Sep 22, 2009
Adjustable transistor body bias circuitry
ALTERA CORP14 citations84
US7514953B2Apr 7, 2009
Adjustable transistor body bias generation circuitry with latch-up prevention
ALTERA CORP14 citations84
US7501849B2Mar 10, 2009
Latch-up prevention circuitry for integrated circuits with transistor body biasing
ALTERA CORP15 citations84
US7495471B2Feb 24, 2009
Adjustable transistor body bias circuitry
ALTERA CORP13 citations84
US7629831B1Dec 8, 2009
Booster circuit with capacitor protection circuitry
ALTERA CORP9 citations79
US7511932B1Mar 31, 2009
ESD protection structure
ALTERA CORP7 citations74
US9496268B2Nov 15, 2016
Integrated circuits with asymmetric and stacked transistors
ALTERA CORP4 citations73
US7957177B2Jun 7, 2011
Static random-access memory with boosted voltages
ALTERA CORP3 citations63
US7782581B1Aug 24, 2010
Method and apparatus for providing electrostatic discharge protection for a polysilicon fuse
ALTERA CORP2 citations63
US10200037B2Feb 5, 2019
Apparatus and methods for on-die temperature sensing to improve FPGA performance
ALTERA CORP0 citations52
US8750026B1Jun 10, 2014
Integrated circuits with asymmetric and stacked transistors
ALTERA CORP1 citations52
PERISETTY SRINIVAS
4 patentsUS9735779B1Aug 15, 2017
Apparatus and methods for on-die temperature sensing to improve FPGA performance
PERISETTY SRINIVAS5 citations83
US8618786B1Dec 31, 2013
Self-biased voltage regulation circuitry for memory
PERISETTY SRINIVAS8 citations81
US8279660B2Oct 2, 2012
Static random-access memory with boosted voltages
PERISETTY SRINIVAS5 citations62
US8099704B1Jan 17, 2012
Performance improvements in an integrated circuit by selectively applying forward bias voltages
PERISETTY SRINIVAS3 citations62