Inventor

HOEKSTRA GEORGE P

US31 patents

⚠️ This page may combine multiple inventors who share the name “HOEKSTRA GEORGE P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOEKSTRA GEORGE P

FREESCALE SEMICONDUCTOR INC

Memory redundancy to replace addresses with multiple errors

Level shifting circuit

Adaptive error correction codes (ECCs) for electronic memories

Dynamic random access memory (DRAM) refresh

Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions

Circuit and method for latch bypass

Double-rate memory

Memory reliability using error-correcting code

Error repair location cache

Error correction with extended CAM

Memory ECC with hard and soft error detection and management

Dynamic latch having integral logic function and method therefor

Memory device with a data hold latch

Domino comparator capable for use in a memory array

Data processing system having translation lookaside buffer valid bits with lock and method therefor

MOTOROLA INC

Hysteresis reduced sense amplifier and method of operation

Randomly accessible memory having time overlapping memory accesses

Bit line precharge in a bimos ram

RAM with dual precharge circuit and write recovery circuitry

Testing arrangement for a DRAM with redundancy

RAMARAJU RAVINDRARAJ

Memory with word line access control

Dynamic logic circuit

Memory column drowsy control

Memory with power savings for unnecessary reads

PELLEY III PERRY H

Dynamic random access memory (DRAM) refresh

Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory

Memory system with error correction and method of operation

HOEKSTRA GEORGE P

Dynamic logic circuit

Error correction with secondary memory

Memory with redundancy

PELLEY PERRY H

Temperature threshold circuit with hysteresis