Inventor

YANG FU-LIANG

TW159 patents

⚠️ This page may combine multiple inventors who share the name “YANG FU-LIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG FU-LIANG

TAIWAN SEMICONDUCTOR MFG

Methods and structures for planar and multiple-gate transistors formed on SOI

Doping of semiconductor fin devices

Silicon-on-insulator chip with multiple crystal orientations

Strained-channel multiple-gate transistor

Semiconductor nano-rod devices

Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices

Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer

Method of forming a transistor with a strained channel

Semiconductor nano-wire devices and methods of fabrication

CMOS inverters configured using multiple-gate transistors

CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Method for dicing semiconductor wafers

Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory

Multiple-gate transistors formed on bulk substrates

Contacts to semiconductor fin devices

Structure and method for forming the gate electrode in a multiple-gate transistor

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

CMOS SRAM cell configured using multiple-gate transistors

Multiple-gate transistors with improved gate control

High performance PD SOI tunneling-biased MOSFET

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Silicon-on-insulator chip with multiple crystal orientations

FinFET transistor device on SOI and method of fabrication

Method of forming DRAM capacitors with protected outside crown surface for more robust structures

Bonded SOI wafer with &lt;100&gt; device layer and &lt;110&gt; substrate for performance improvement

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Multiple-gate transistors formed on bulk substrates

Methods and structures for planar and multiple-gate transistors formed on SOI

Multiple-gate transistor structure

Gate electrode for a semiconductor fin device

Semiconductor-on-insulator (SOI) strained active area transistor

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Structure and method for forming the gate electrode in a multiple-gate transistor

Contacts to semiconductor fin devices

Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement

Gate electrode for a semiconductor fin device

Silicon-on-insulator ULSI devices with multiple silicon film thicknesses

Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement

Semiconductor chip with gate dielectrics for high-performance and low-leakage applications

Semiconductor diodes with fin structure

VANGUARD INT SEMICONDUCT CORP

Method for simultaneously fabricating a DRAM capacitor and metal interconnections

Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device

Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process

Method of forming an isolation region in a semiconductor substrate

Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory

Method of fabricating single crown, extendible to triple crown, stacked capacitor structures, using a self-aligned capacitor node contact

Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures

Method of forming shallow trench isolation structure

Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode

LEE TSUNG-LIN

Integrated circuit structures with multiple FinFETs

Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement