Inventor

SU KE-WEI

TW24 patents

⚠️ This page may combine multiple inventors who share the name “SU KE-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SU KE-WEI

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated circuit layout generation method and system

Integrated circuit modeling methods and systems

High sensitivity ISFET sensor

Method and system for integrated circuit design with on-chip variation and spatial correlation

Method for analyzing interconnect process variation

Simulation scheme including self heating effect

Biosensor

Integrated circuit layout generation method and system

Integrated circuit layout generation method and system

Integrated circuit layout generation method

Integrated circuit layout generation method

Integrated circuit layout generation method and system

Method for establishing aging model of device and analyzing aging state of device with aging model

Method of designing circuit layout and system for implementing the same

Device and method for detecting miniature targets in a fluid sample

Semiconductor structure having biosensor and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Method and system for integrated circuit design with on-chip variation and spatial correlation

TAIWAN SEMICONDUCTOR MFG

Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits

Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof

Characterization methodology for the thin gate oxide device

Constructing mapping between model parameters and electrical parameters

Circuit simulation with rule check for device

LO JIA-LIN

Circuit device reliability simulation system