Inventor

REINHARDT STEVEN K

US25 patents

⚠️ This page may combine multiple inventors who share the name “REINHARDT STEVEN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REINHARDT STEVEN K

INTEL CORP

Incremental checkpointing in a multi-threaded architecture

Hardware recovery in a multi-threaded architecture

Periodic checkpointing in a redundantly multi-threaded architecture

Method and apparatus for reducing false error detection in a redundant multi-threaded system

Implementing check instructions in each thread within a redundant multithreading environments

Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support

Fault detection using redundant virtual machines

Method and apparatus for reducing false error detection in a microprocessor

Reducing false error detection in a microprocessor by tracking instructions neutral to errors

ADVANCED MICRO DEVICES INC

GPU remote communication with triggered operations

Message aggregation, combining and compression for efficient data communications in GPU-based clusters

Method for memory consistency among heterogeneous computer components

Conditional atomic operations in single instruction multiple data processors

Conditional notification mechanism

Remote task queuing by networked computing devices

Network interface controller-based scheduling of processing tasks in a distributed computing system

Wavefront resource virtualization

Conditional notification mechanism

HEWLETT PACKARD DEVELOPMENT CO

Simultaneous and redundantly threaded processor store instruction comparator

Input replicator for interrupts in a simultaneous and redundantly threaded processor

Active load address buffer

WISCONSIN ALUMNI RES FOUND

Cacheable interface control registers for high speed data transfer

BECKMANN BRADFOD M

Dual-granularity state tracking for directory-based cache coherence

KRISHNA TUSHAR

Message broadcast with router bypassing

BECKMANN BRADFORD M

Simulating vector execution