Inventor

HALLER GORDON

US42 patents

⚠️ This page may combine multiple inventors who share the name “HALLER GORDON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HALLER GORDON

MICRON TECHNOLOGY INC

Integrated circuits and methods of forming a field effect transistor

One-transistor memory cell with bias gate

Transistor devices, transistor structures and semiconductor constructions

Method of forming contact plugs

Methods of fabricating fin structures

System and method for fabricating a fin field effect transistor

Method to form a corrugated structure for enhanced capacitance

Self-aligned contact plugs

Semiconductor memory device

Drain select gate formation methods and apparatus

Transistors

Method to form a corrugated structure for enhanced capacitance

Method to form a corrugated structure for enhanced capacitance with plurality of boro-phospho silicate glass including germanium

Semiconductor devices and methods of fabrication

Semiconductor devices and methods of fabrication

Semiconductor devices and methods of fabrication

Integrated circuits

Forming terminations in stacked memory arrays

Semiconductor devices and methods of fabrication

Formation of termination structures in stacked memory arrays

Forming terminations in stacked memory arrays

Formation of termination structures in stacked memory arrays

Methods of fabricating a memory device

Semiconductor devices including WiSX

Drain select gate formation methods and apparatus

Methods of forming semiconductor constructions

Integrated circuits and methods of forming a field effect transistor

Forming air gaps in memory arrays and memory arrays with air gaps thus formed

Method of making a semiconductor device

Method and apparatus for a two-step resist soft bake to prevent ILD outgassing during semiconductor processing

System for two-step resist soft bake to prevent ILD outgassing during semiconductor processing

Forming source/drain zones with a dielectric plug over an isolation region between active regions

INTEL CORP

Memory devices and systems having reduced bit line to drain select gate shorting and associated methods

Memory devices and systems having reduced bit line to drain select gate shorting and associated methods

Method, apparatus, and system for flash memory

TANG SAHN D

Fin structures and methods of fabricating fin structures

TANG SANH D

Methods of fabricating fin structures

MICRON TECHNOLGY INC

Contact plug

MATHEW JAMES

Forming air gaps in memory arrays and memory arrays with air gaps thus formed

HALLER GORDON

Methods of fabricating a memory device

HOPKINS JOHN

Source/drain zones with a delectric plug over an isolation region between active regions and methods

FAN DARWIN

Methods of tunnel oxide layer formation in 3D NAND memory structures and associated devices