Inventor
LA ROSA GIUSEPPE
US10 patents
Patents
10 patentsUS6521469B1Feb 18, 2003
Line monitoring of negative bias temperature instabilities by hole injection methods
IBM63 citations94
US6049495AApr 11, 2000
Auto-programmable current limiter to control current leakage due to bitline to wordline short
IBM26 citations92
US7710141B2May 4, 2010
Method and apparatus for dynamic characterization of reliability wearout mechanisms
IBM14 citations83
US7375371B2May 20, 2008
Structure and method for thermally stressing or testing a semiconductor device
IBM9 citations80
US6724053B1Apr 20, 2004
PMOSFET device with localized nitrogen sidewall implantation
IBM12 citations73
US6348394B1Feb 19, 2002
Method and device for array threshold voltage control by trapped charge in trench isolation
IBM7 citations73
US6958621B2Oct 25, 2005
Method and circuit for element wearout recovery
IBM7 citations68
US7023041B2Apr 4, 2006
Trench capacitor vertical structure
IBM6 citations63
US7805274B2Sep 28, 2010
Structure and methodology for characterizing device self-heating
IBM4 citations61
US9882377B2Jan 30, 2018
Electrostatic discharge protection solutions
IBM1 citations52