Inventor

TEMAM OLIVIER

FR47 patents

⚠️ This page may combine multiple inventors who share the name “TEMAM OLIVIER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEMAM OLIVIER

GOOGLE LLC

Neural network compute tile

Permuting in a matrix-vector processor

Neural network crossbar stack

Neural network accelerator with parameters resident on chip

Neural network instruction set architecture

Accessing data in multi-dimensional tensors using adders

Yield improvements for three-dimensionally stacked neural network accelerators

Permuting in a matrix-vector processor

Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies

Accessing prologue and epilogue data

Accessing data in multi-dimensional tensors using adders

Hardware double buffering using a special purpose computational unit

Alternative loop limits for accessing data in multi-dimensional tensors

Accessing prologue and epilogue data

Neural network instruction set architecture

Neural network compute tile

Neural network instruction set architecture

Special purpose neural network training chip

Vector reduction processor

Permuting in a matrix-vector processor

Permuting in a matrix-vector processor

Permuting in a matrix-vector processor

Hardware double buffering using a special purpose computational unit

Vector reduction processor

Vector reduction processor

Vector reduction processor

Special purpose neural network training chip

Neural network compute tile

Permuting in a matrix-vector processor

Yield improvements for three-dimensionally stacked neural network accelerators

Yield improvements for three-dimensionally stacked neural network accelerators

Neural network compute tile

Permuting in a matrix-vector processor

Neural network accelerator with parameters resident on chip

Neural network accelerator with parameters resident on chip

Hardware double buffering using a special purpose computational unit

Alternative loop limits for accessing data in multi-dimensional tensors

Accelerating neural networks in hardware using interconnected crossbars

Neural network crossbar stack

Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies

Accelerating neural networks in hardware using interconnected crossbars

Neural network accelerator tile architecture with three-dimensional stacking

Neural network crossbar stack

Vector reduction processor

GOOGLE INC

Neural network instruction set architecture

Neural network compute tile

Neural network accelerator tile architecture with three-dimensional stacking