Inventor

SHARMA DEBENDRA DAS

US62 patents

⚠️ This page may combine multiple inventors who share the name “SHARMA DEBENDRA DAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHARMA DEBENDRA DAS

INTEL CORP

Providing high availability in a PCI-Express link in the presence of lane faults

High performance interconnect physical layer

Out-of-order servicing of read requests with minimal additional storage

Method and apparatus for improving high availability in a PCI express link through predictive failure analysis

Fast deskew when exiting low-power partial-width high speed link state

Link and lane level packetization scheme of encoding in serial links

Point-to-point link negotiation method and apparatus

Method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link

Low latency retimer

High performance interconnect

NoDMA cache

Adjustable retimer buffer

Multiple uplink port devices

Low power entry in a shared memory link

High performance interconnect physical layer

High performance interconnect physical layer

Using information provided through tag space

Sharing memory and I/O services between nodes

Extending multichip package link off package

Adjustable retimer buffer

HEWLETT PACKARD DEVELOPMENT CO

Apparatus and method for ensuring forward progress in coherent I/O systems

CRC encoding scheme for conveying status information

Method and apparatus for improving system performance through remote credit management

Multiple ECC schemes to improve bandwidth

Multiple ECC schemes to improve bandwidth

Credit initialization in systems with proactive flow control

Method for assigning addresses to input/output devices

Arbitration scheme for equitable distribution of bandwidth for agents with different bandwidth requirements

Reconfigurable FIFO interface to support multiple channels in bundled agent configurations

Method and apparatus for preventing underflow and overflow across an asynchronous channel

Method and apparatus for verifying error correcting codes

Using read current transactions for improved performance in directory-based coherent I/O systems

Apparatus and method using sub-cacheline transactions to improve system performance

Directory-based cache coherency scheme for reducing memory bandwidth loss

ECC code mechanism to detect wire stuck-at faults

System and method for input/output module virtualization and memory interleaving using cell map

System and method for memory migration in distributed-memory multi-processor systems

HEWLETT PACKARD CO

ECC code mechanism to detect wire stuck-at faults

Using page registers for efficient communication

Method and apparatus for using the unused bits of a data packet to transmit additional information

Verification of cache prefetch mechanism

Method and apparatus for evaluating a circuit

System and method for efficient communication between buses

Formal verification of queue flow-control through model-checking

AJANOVIC JASMIN

PCI express enhancements and extensions

PCI express enhancements and extensions

Atomic operations

IYER VENKATRAMAN

Embedded control channel for high speed serial interconnect

HEWLETT PACKARD DEV COMPANAY L

Verification of asynchronous boundary behavior

SINGHAL ABHISHEK

Multiple compression techniques for packetized information