Inventor

ROESNER WOLFGANG

DE174 patents

⚠️ This page may combine multiple inventors who share the name “ROESNER WOLFGANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROESNER WOLFGANG

IBM

Method and system for counting events within a simulation model

Method and system for instrumenting simulation models

Method and system for selectively disabling simulation model instrumentation

Method, system and program product providing a configuration specification language having clone latch support

Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities

Method, system and program product providing a configuration specification language having split latch support

Method, system and program product for specifying and using register entities to configure a simulated or physical digital system

Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs

Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language

C-API instrumentation for HDL models

Method, system and program product for configuring a simulation model of a digital design

Dynamic loading of C-API HDL model instrumentation

Count data access in a distributed simulation environment

Method, system and program product for utilizing a configuration database to configure a hardware digital system

Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs

Automatic adjustment for counting instrumentation

Hardware simulator instrumentation

Accurately modeling an asynchronous interface using expanded logic elements

System and method for accurately modeling an asynchronous interface using expanded logic elements

Method and system for incrementally compiling instrumentation into a simulation model

Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip

Method, system and program product supporting user tracing in a simulator

Method and system for reducing storage requirements of simulation data via KEYWORD restrictions

INFINEON TECHNOLOGIES AG

High-density NROM-FINFET

Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor

Memory cell configuration, method for fabricating it and methods for operating it

Method of producing a memory cell configuration

Charge-trapping memory cell and method for production

DRAM cell circuit

DRAM cell configuration and method for its production

Integrated circuit arrangement with capacitor and fabrication method

DRAM memory cell

Integrated circuit arrangement with capacitor

Nonvolatile semiconductor memory cell and method for fabricating the memory cell

Memory cell configuration, magnetic ram, and associative memory

Integrated circuit with vertical transistors

SIEMENS AG

Method of producing a read-only storage cell arrangement

Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production

Method for producing a vertical MOS-transistor

Process of making a dram cell arrangement

Read-only memory cell arrangement and method for its production

High density read only memory cell configuration and method for its production

DRAM cell arrangement and method for its manufacture

Microelectronic component

Process for producing storage capacitors for DRAM cells

Method for producing an opening in a layered semiconductor structure or a contact hole in an integrated circuit or DRAM

Method of forming DRAM cell arrangement

Method for manufacturing vertical MOS transistors

INFINEON TECHNOLOGIES INC

Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell

QIMONDA AG

Integrated circuit including a vertical transistor and method