Inventor

CHEUNG ROBIN

US55 patents

⚠️ This page may combine multiple inventors who share the name “CHEUNG ROBIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEUNG ROBIN

APPLIED MATERIALS INC

In-situ electroless copper seed layer enhancement in an electroplating system

Method for achieving copper fill of high aspect ratio interconnect features

Electro-chemical deposition system

Apparatus for electro-chemical deposition with thermal anneal chamber

Method of treating a substrate

Method of forming copper interconnects

Method and apparatus for heating and cooling substrates

Method and apparatus for heating and cooling substrates

Electro-chemical deposition system

Method and apparatus for treating a substrate

Method and apparatus for heating and cooling substrates

Method for heating and cooling substrates

Method and apparatus for heating and cooling substrates

Method and apparatus for providing intra-tool monitoring and control

Electroless deposition method over sub-micron apertures

Electro-chemical deposition system

Method and apparatus for annealing copper films

Post metal barrier/adhesion film

Integrated solder bump deposition apparatus and method

Method and apparatus for improved electroplating fill of an aperture

Method and apparatus for providing intra-tool monitoring and control

Methods for post-etch deposition of a dielectric film

Method of conditioning electrochemical baths in plating technology

ADVANCED MICRO DEVICES INC

Method for filling a dual damascene opening having high aspect ratio to minimize electromigration failure

Method of electroplating a copper or copper alloy interconnect

Simplified dual damascene process for multi-level metallization and interconnection structure

Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines

Bias plasma deposition for selective low dielectric insulation

Self-aligning vias for semiconductors

Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug

Scaled interconnect anodization for high frequency applications

Bias plasma deposition for selective low dielectric insulation

Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines

Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device

Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines

Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device

Scaled interconnect anodization for high frequency applications

Cure process for manufacture of low dielectric constant interlevel dielectric layers

Method for manufacturing semiconductors with self-aligning vias

Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines

Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device

Construction that prevents the undercut of interconnect lines in plasma metal etch systems

UNITY SEMICONDUCTOR CORP

Continuous plane of thin-film materials for a two-terminal cross-point memory

Memory cell formation using ion implant isolated conductive metal oxide

Continuous plane of thin-film materials for a two-terminal cross-point memory

Continuous plane of thin-film materials for a two-terminal cross-point memory

CHEUNG ROBIN

Continuous plane of thin-film materials for a two-terminal cross-point memory

Immersion platinum plating solution

RINERSON DARRELL

Device fabrication

Device fabrication