P

Inventor

KALLA RONALD N

US20 patents

Patents

20 patents
US5224213AJun 29, 1993

Ping-pong data buffer for transferring data from one data bus to another data bus

IBM133 citations97
US5471626ANov 28, 1995

Variable stage entry/exit instruction pipeline

IBM59 citations95
US7013400B2Mar 14, 2006

Method for managing power in a simultaneous multithread processor by loading instructions into pipeline circuit during select times based on clock signal frequency and selected power mode

IBM27 citations87
US8356151B2Jan 15, 2013

Reporting of partially performed memory move

IBM7 citations84
US7949859B2May 24, 2011

Mechanism for avoiding check stops in speculative accesses while operating in real mode

IBM13 citations84
US7937570B2May 3, 2011

Termination of in-flight asynchronous memory move

IBM14 citations84
US7370177B2May 6, 2008

Mechanism for avoiding check stops in speculative accesses while operating in real mode

IBM15 citations84
US7363625B2Apr 22, 2008

Method for changing a thread priority in a simultaneous multithread processor

IBM9 citations84
US7469407B2Dec 23, 2008

Method for resource balancing using dispatch flush in a simultaneous multithread processor

IBM13 citations83
US7213135B2May 1, 2007

Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions

IBM11 citations83
US10831889B2Nov 10, 2020

Secure memory implementation for secure execution of virtual machines

IBM1 citations73
US10474816B2Nov 12, 2019

Secure memory implementation for secure execution of Virtual Machines

IBM2 citations73
US10296741B2May 21, 2019

Secure memory implementation for secure execution of virtual machines

IBM4 citations73
US8387065B2Feb 26, 2013

Speculative popcount data creation

IBM2 citations63
US6981128B2Dec 27, 2005

Atomic quad word storage in a simultaneous multithreaded system

IBM5 citations60
US10671537B2Jun 2, 2020

Reducing translation latency within a memory management unit using external caching structures

IBM0 citations52
US10649902B2May 12, 2020

Reducing translation latency within a memory management unit using external caching structures

IBM0 citations52
US7996564B2Aug 9, 2011

Remote asynchronous data mover

IBM1 citations52
US8650442B2Feb 11, 2014

Programming in a simultaneous multi-threaded processor environment

IBM0 citations49
US8356210B2Jan 15, 2013

Programming in a simultaneous multi-threaded processor environment including permitting apparently exclusive access to multiple threads and disabling processor features during thread testing

IBM0 citations49