Inventor

LEVITAN DAVID S

US47 patents

⚠️ This page may combine multiple inventors who share the name “LEVITAN DAVID S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEVITAN DAVID S

IBM

Method and system for enhanced branch history prediction accuracy in a superscalar processor system

System and method for optimizing branch logic for handling hard to predict indirect branches

Branch target address cache

Apparatus and computer program product for testing ability to recover from cache directory errors

Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache

Counter register implementation for speculative execution of branch on count instructions

Method and system for single cycle dispatch of multiple instructions in a superscalar processor system

Branch prediction using multiple versions of history data

Branch target address cache selectively applying a delayed hit

Branch prediction with partially folded global history vector for reduced XOR operation time

Method for resource balancing using dispatch flush in a simultaneous multithread processor

Techniques for dynamic sequential instruction prefetching

Power management of branch predictors in a computer processor

Power management of branch predictors in a computer processor

Predicting indirect branches using problem branch filtering and pattern cache

Branch prediction using multiple versions of history data

Hardware-assisted program trace collection with selectable call-signature capture

Saving power by powering down an instruction fetch array based on capacity history of instruction buffer

Branch target address cache with hashed indices

Branch target address cache including address type tag bit

Dynamic sequential instruction prefetching

Compressed indirect prediction caches

Instruction prefetching in a computer processor using a prefetch prediction vector

Branch prediction using multiple versions of history data

Branch prediction using multiple versions of history data

Identifying and tagging breakpoint instructions for facilitation of software debug

Identifying and tagging breakpoint instructions for facilitation of software debug

Selectively supporting static branch prediction settings only in association with processor-designated types of instructions

Instruction prefetching in a computer processor using a prefetch prediction vector

Variable latency flush filtering

Managing an effective address table in a multi-slice processor

Managing an effective address table in a multi-slice processor

Power management of branch predictors in a computer processor

Generating a mask vector for determining a processor instruction address using an instruction tag in a multi-slice processor

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

Branch target address cache storing direct predictions

Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction

Techniques for predicting a target address of an indirect branch instruction

Blocking instruction fetching in a computer processor

Tracking long GHV in high performance out-of-order superscalar processors

Branch prediction in a computer processor

KONIGSBURG BRIAN R

Reducing store-hit-loads in an out-of-order processor

MOTOROLA INC

Data processor with programmable levels of speculative instruction fetching and method of operation

EKANADHAM KATTAMURI

Operating a stack of information in an information handling system

DOING RICHARD W

Tracking effective addresses in an out-of-order processor

LEVENSTEIN SHELDON B

Controlling power of a cache based on predicting the instruction cache way for high power applications

FRAZIER GILES R

Task switch immunized performance monitoring