Inventor
WARD III JOHN W
US9 patents
⚠️ This page may combine multiple inventors who share the name “WARD III JOHN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
7 patentsUS7013400B2Mar 14, 2006
Method for managing power in a simultaneous multithread processor by loading instructions into pipeline circuit during select times based on clock signal frequency and selected power mode
IBM27 citations87
US7769984B2Aug 3, 2010
Dual-issuance of microprocessor instructions using dual dependency matrices
IBM9 citations83
US7469407B2Dec 23, 2008
Method for resource balancing using dispatch flush in a simultaneous multithread processor
IBM13 citations83
US7213135B2May 1, 2007
Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions
IBM11 citations83
US7822954B2Oct 26, 2010
Methods, systems, and computer program products for recovering from branch prediction latency
IBM2 citations63
US7549095B1Jun 16, 2009
Error detection enhancement in a microprocessor through the use of a second dependency matrix
IBM4 citations62
US9342307B2May 17, 2016
Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions
IBM0 citations51
ALEXANDER GREGORY W
2 patentsUS8661230B2Feb 25, 2014
Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions
ALEXANDER GREGORY W5 citations83
US9069546B2Jun 30, 2015
Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions
ALEXANDER GREGORY W4 citations72