Inventor

GAMBINO JEFFREY P

US482 patents

⚠️ This page may combine multiple inventors who share the name “GAMBINO JEFFREY P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAMBINO JEFFREY P

IBM

Low-K gate spacers by fluorine implantation

Fin field effect transistor with self-aligned gate

Semiconductor device of an embedded DRAM on SOI substrate

Embedded DRAM on silicon-on-insulator substrate

Backside device contact

On-chip embedded thermal antenna for chip cooling

CMOS imager array with recessed dielectric

Bond pad for wafer and package for CMOS imager

Electrical interconnection structure formation

Damascene copper wiring image sensor

Transistors having independently adjustable parameters

Power transistor having vertical FETs and method for making same

Method of forming a capacitor and a capacitor formed using the method

Anti-reflection structures for CMOS image sensors

Device and methodology for reducing effective dielectric constant in semiconductor devices

Integrated circuit having a via and a capacitor

Shallow trench isolation method utilizing combination of spacer and fill

Conductor-insulator-conductor structure

Raised source/drain using recess etch of polysilicon

Crown capacitor using a tapered etch of a damascene lower electrode

Self-aligned contact wiring process for SI devices

Method of chemically mechanically polishing an electronic component

Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics

Electrically programmable antifuse using metal penetration of a junction

Crack stop for low K dielectrics

Charge modulation network for multiple power domains for silicon-on-insulator technology

Low temperature emitter process for high performance bipolar devices

Biological and chemical sensors

Conductive pillar shaped for solder confinement

Photodiode structures

Backside contact to final substrate

Semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure

Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation

Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via

Methods for forming anti-reflection structures for CMOS image sensors

Bonded semiconductor substrate including a cooling mechanism

Device and methodology for reducing effective dielectric constant in semiconductor devices

Undercut-free BLM process for Pb-free and Pb-reduced C4

CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom

Structure and method for self aligned vertical plate capacitor

Air-gap insulated interconnections

Air gap under on-chip passive device

Deep trench contact and isolation of buried photodetectors

Image sensor including spatially different active and dark pixel interconnect patterns

Stacked imager package

Undercut-free BLM process for Pb-free and Pb-reduced C4

DAUBENSPECK TIMOTHY H

Structure and method of making an offset-trench crackstop that forms an air gap adjacent to a passivated metal crackstop

Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump

CORNELL RES FOUNDATION INC

Self-aligned process for capping copper lines

GLOBALFOUNDRIES INC

Multi-chip modules with vertically aligned grating couplers for transmission of light signals between optical waveguides