Inventor

RADIGAN STEVEN J

US36 patents

⚠️ This page may combine multiple inventors who share the name “RADIGAN STEVEN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RADIGAN STEVEN J

SANDISK 3D LLC

Nonvolatile memory cell comprising a reduced height vertical diode

Conductive hard mask to protect patterned features during trench etch

Nonvolatile memory cell comprising a reduced height vertical diode

Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure

Method for fabricating self-aligned complementary pillar structures and wiring

Methods for increased array feature density

Method of making damascene diodes using sacrificial material

Method for fabricating pitch-doubling pillar structures

Concave word line and convex interlayer dielectric for protecting a read/write layer

Patterning method for high density pillar structures

Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon

Imaging post structures using x and y dipole optics and a single mask

Resist feature and removable spacer pitch doubling patterning method for pillar structures

Methods for increased array feature density

Resist feature and removable spacer pitch doubling patterning method for pillar structures

Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure

Ultrashallow semiconductor contact by outdiffusion from a solid source

Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon

Patterning method for high density pillar structures

Imaging post structures using X and Y dipole optics and a single mask

Method for reducing pillar structure dimensions of a semiconductor device

Methods for protecting patterned features during trench etch

Nonvolatile memory cell comprising a reduced height vertical diode

Method for cleaning slurry particles from a surface polished by chemical mechanical polishing

NGUYEN NATALIE

Three dimensional horizontal diode non-volatile memory array and method of making thereof

Patterning method for high density pillar structures

Patterning method for high density pillar structures

CHEN YUNG-TIN

Method of making pillars using photoresist spacer mask

Resist feature and removable spacer pitch doubling patterning method for pillar structures

MATRIX SEMICONDUCTOR INC

Metal structures for integrated circuits and methods for making the same

XU HUIWEN

Methods for increased array feature density

FAIRCHILD CAMERA INSTR CO

Process for patterning metal connections on a semiconductor structure by using an aluminum oxide etch resistant layer

SANDISK TECHNOLOGIES INC

Method for using nanoparticles to make uniform discrete floating gate layer

HERNER SCOTT BRAD

Method for forming a nonvolatile memory cell comprising a reduced height vertical diode

TANAKA YOICHIRO

Liner for tungsten/silicon dioxide interface in memory

CANDESCENT TECH CORP

Structure, fabrication, and corrective test of electron-emitting device having electrode configured to reduce cross-over capacitance and/or facilitate short-circuit repair