Inventor

ANG CHEW HOE

SG29 patents

⚠️ This page may combine multiple inventors who share the name “ANG CHEW HOE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANG CHEW HOE

CHARTERED SEMICONDUCTOR MFG

Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth

Method for forming L-shaped spacers with precise width control

Method of fabricating variable length vertical transistors

Test structure for automatic dynamic negative-bias temperature instability testing

Method for forming high-K charge storage device

Method to fabricate Ge and Si devices together for performance enhancement

High K artificial lattices for capacitor applications to use in CU or AL BEOL

Method of forming a high performance and low cost CMOS device

Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape

Triple gate oxide process with high-k gate dielectric

Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide

Method of fabricating CMOS device with dual gate electrode

Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization

Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing

Method to fabricate a single gate with dual work-functions

Forming dual gate oxide thickness on vertical transistors by ion implantation

Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate

Ultra-thin gate oxide through post decoupled plasma nitridation anneal

Method of fabricating CMOS device with dual gate electrode

Test structure for automatic dynamic negative-bias temperature instability testing

Method of forming shallow trench isolation regions with improved corner rounding

Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask

Charge pump current source

High K artificial lattices for capacitor applications to use in Cu or Al BEOL

Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers

Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration

Semiconductor device and fabrication method

Method to pattern small features by using a re-flowable hard mask

ADVANCED MICRO DEVICES INC

Method and apparatus for monitoring endcap pullback