Inventor
PATEL RAJESH BHIKHUBHAI
US16 patents
⚠️ This page may combine multiple inventors who share the name “PATEL RAJESH BHIKHUBHAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
15 patentsUS5860107AJan 12, 1999
Processor and method for store gathering through merged store operations
IBM57 citations96
US5802572ASep 1, 1998
Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache
IBM90 citations96
US5872948AFeb 16, 1999
Processor and method for out-of-order execution of instructions based upon an instruction parameter
IBM23 citations92
US5809526ASep 15, 1998
Data processing system and method for selective invalidation of outdated lines in a second level memory in response to a memory request initiated by a store operation
IBM35 citations92
US5802556ASep 1, 1998
Method and apparatus for correcting misaligned instruction data
IBM30 citations92
US5765191AJun 9, 1998
Method for implementing a four-way least recently used (LRU) mechanism in high-performance
IBM20 citations92
US5737751AApr 7, 1998
Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system
IBM29 citations92
US5873123AFeb 16, 1999
Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries
IBM39 citations89
US5737749AApr 7, 1998
Method and system for dynamically sharing cache capacity in a microprocessor
IBM40 citations88
US5787479AJul 28, 1998
Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation
IBM17 citations83
US5974505AOct 26, 1999
Method and system for reducing power consumption of a non-blocking cache within a data processing system
IBM15 citations73
US5895486AApr 20, 1999
Method and system for selectively invalidating cache lines during multiple word store operations for memory coherence
IBM11 citations73
US5721867AFeb 24, 1998
Method and apparatus for executing single beat write store instructions during a cache store linefill operation
IBM7 citations73
US5758117AMay 26, 1998
Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor
IBM5 citations63
US5764940AJun 9, 1998
Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetch
IBM3 citations62