P

Inventor

CHEE CHOONG KOOI

MY26 patents
⚠️ This page may combine multiple inventors who share the name “CHEE CHOONG KOOI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

23 patents
US10903142B2Jan 26, 2021

Micro through-silicon via for transistor density scaling

INTEL CORP8 citations83
US7212332B2May 1, 2007

Micro-electromechanical system (MEMS) polyelectrolyte gel network pump

INTEL CORP11 citations83
US7151014B2Dec 19, 2006

Underfilling process in a molded matrix array package using flow front modifying solder resist

INTEL CORP12 citations83
US7005321B2Feb 28, 2006

Stress-compensation layers in contact arrays, and processes of making same

INTEL CORP11 citations83
US7339276B2Mar 4, 2008

Underfilling process in a molded matrix array package using flow front modifying solder resist

INTEL CORP5 citations73
US6774471B2Aug 10, 2004

Protected bond fingers

INTEL CORP10 citations73
US11652026B2May 16, 2023

Micro through-silicon via for transistor density scaling

INTEL CORP2 citations72
US11398415B2Jul 26, 2022

Stacked through-silicon vias for multi-device packages

INTEL CORP3 citations72
US7088010B2Aug 8, 2006

Chip packaging compositions, packages and systems made therewith, and methods of making same

INTEL CORP7 citations71
US7262077B2Aug 28, 2007

Capillary underfill and mold encapsulation method and apparatus

INTEL CORP9 citations64
US12112997B2Oct 8, 2024

Micro through-silicon via for transistor density scaling

INTEL CORP0 citations62
US12080628B2Sep 3, 2024

Micro through-silicon via for transistor density scaling

INTEL CORP0 citations62
US11393741B2Jul 19, 2022

Micro through-silicon via for transistor density scaling

INTEL CORP0 citations62
US12237245B2Feb 25, 2025

Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same

INTEL CORP0 citations61
US11107751B2Aug 31, 2021

Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same

INTEL CORP0 citations61
US11805602B2Oct 31, 2023

Chip assemblies

INTEL CORP0 citations60
US8384223B2Feb 26, 2013

Backside mold process for ultra thin substrate and package on package assembly

INTEL CORP2 citations54
US7453622B2Nov 18, 2008

Micro-electromechanical system (mems) polyelectrolyte gel network pump

INTEL CORP0 citations51
US11527481B2Dec 13, 2022

Stacked semiconductor package with flyover bridge

INTEL CORP0 citations50
US11562959B2Jan 24, 2023

Embedded dual-sided interconnect bridges for integrated-circuit packages

INTEL CORP0 citations49
US8835220B2Sep 16, 2014

Backside mold process for ultra thin substrate and package on package assembly

INTEL CORP0 citations43
US10136516B2Nov 20, 2018

Microelectronic device attachment on a reverse microelectronic package

INTEL CORP0 citations41
US9159714B2Oct 13, 2015

Package on wide I/O silicon

INTEL CORP0 citations41

ALTERA CORP

2 patents

LOO HOWE YIN

1 patent