Inventor · disambiguated record
Dilip Vijay
Also filed as: VIJAY DILIP · VIJAY DILIP P
12 granted patents·1 pending application·257 citations·filing 1993–2013
91Inventor score
Top patents by PatentIndex Score
13 records- 0189US5790366AHigh temperature electrode-barriers for ferroelectric and other capacitor structuresSHARP KK·Filed 1996·Granted Aug 4, 1998·77 cites·14 claims
- 0286US5807774ASimple method of fabricating ferroelectric capacitorsSHARP KK·Filed 1996·Granted Sep 15, 1998·70 cites·14 claims
- 0379US5491102AMethod of forming multilayered electrodes for ferroelectric devices consisting of conductive layers and interlayers formed by chemical reactionCERAM INC·Filed 1993·Granted Feb 13, 1996·47 cites·8 claims
- 0476US7205673B1Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processingLSI LOGIC CORP·Filed 2005·Granted Apr 17, 2007·7 cites·3 claims
- 0574US6713386B1Method of preventing resist poisoning in dual damascene structuresLSI LOGIC CORP·Filed 2001·Granted Mar 30, 2004·17 cites·4 claims
- 0672US8552560B2Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processingBHATT HEMANSHU·Filed 2005·Granted Oct 8, 2013·7 cites·3 claims
- 0770US7531442B2Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processingLSI CORP·Filed 2005·Granted May 12, 2009·5 cites·4 claims
- 0855US7354790B2Method and apparatus for avoiding dicing chip-outs in integrated circuit dieLSI LOGIC CORP·Filed 2005·Granted Apr 8, 2008·2 cites·18 claims
- 0953US6139780ADynamic random access memories with dielectric compositions stable to reductionSHARP KK·Filed 1998·Granted Oct 31, 2000·20 cites·2 claims
- 1051US6969683B2Method of preventing resist poisoning in dual damascene structuresLSI LOGIC CORP·Filed 2003·Granted Nov 29, 2005·3 cites·16 claims
- 1150US2014030541A1Alternate pad structures/passivation integration schemes to reduce or eliminate imc cracking in post wire bonded dies during cu/low-k beol processingLSI CORP·Filed 2013·Application pending·0 cites
- 1240US8076779B2Reduction of macro level stresses in copper/low-K wafersSUN SEY-SHING·Filed 2005·Granted Dec 13, 2011·0 cites·4 claims
- 1329US5496437AReactive ion etching of lead zirconate titanate and ruthenium oxide thin filmsCERAM INC·Filed 1993·Granted Mar 5, 1996·2 cites·10 claims
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