Inventor

LU SHIH-LIEN L

US72 patents

⚠️ This page may combine multiple inventors who share the name “LU SHIH-LIEN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU SHIH-LIEN L

INTEL CORP

Floating-body memory cell write

Noise suppression for open bit line DRAM architectures

Low-leakage MOS planar capacitors for use within DRAM storage cells

One-transistor and one-capacitor DRAM cell for logic process technology

Error detection and correction apparatus and method

Selective error correction in memory to reduce power consumption

Non-stalling circular counterflow pipeline processor with reorder buffer

Bitcell state retention

Apparatus, system and method for determining comparison information based on memory data

Write operations in spin transfer torque memory

2-transistor floating-body dram

Systolic memory arrays

1P1N 2T gain cell

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Register files and caches with digital sub-threshold leakage current calibration

Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports

Frequency phase detector for differentiating frequencies having small phase differences

Noise suppression for open bit line DRAM architectures

Method, system and apparatus for detecting and recovering from timing errors

Hiding refresh of memory and refresh-hidden memory

Non-stalling circular counterflow pipeline processor with recorder buffer

Register file scheme

Register file scheme

Non-stalling circular counterflow pipeline processor with reorder buffer

Non-stalling circular counterflow pipeline processor with reorder buffer

Techniques to reduce memory cell refreshes for a memory device

DRAM data path sharing via a split local data bus

Apparatus and method for page copying within sections of a memory

Two transistor gain cell, method, and system

Modified least recently allocated cache replacement method and apparatus that allows skipping a least recently allocated cache block

Double data rate dynamic logic

Delay fault detection using latch with error sampling

Method and apparatus for late timing transition detection

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

High voltage driver

Flip-flop circuit

Multiple word-line accessing and accessor

DRAM data path sharing via a segmented global data bus

DRAM data path sharing via a split local data bus and a segmented global data bus

Apparatus and method for detecting single flip-error in a complementary resistive memory

Apparatus to reduce retention failure in complementary resistive memory

Bitcell state retention

Non-stalling circular counterflow pipeline processor with reorder buffer

Non-stalling circular counterflow pipeline processor with reorder buffer

Sequential circuit with error detection

NAEIMI HELIA

Resistive memory write operation with merged reset

LU SHIH-LIEN L

Low overhead error correcting code protection for stored information

WU WEI

Method of correcting adjacent errors by using BCH-based error correction coding

GROCHOWSKI EDWARD

Method and apparatus for late timing transition detection

BOWMAN KEITH

Sequential circuit with error detection