Inventor
MARCHAND PATRICK R
US50 patents
⚠️ This page may combine multiple inventors who share the name “MARCHAND PATRICK R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLASCO DAVID B
16 patentsUS8868838B1Oct 21, 2014
Multi-class data cache policies
GLASCO DAVID B67 citations98
US8244984B1Aug 14, 2012
System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy
GLASCO DAVID B53 citations94
US8271734B1Sep 18, 2012
Method and system for converting data formats using a shared cache coupled between clients and an external memory
GLASCO DAVID B25 citations92
US8135926B1Mar 13, 2012
Cache-based control of atomic operations in conjunction with an external ALU block
GLASCO DAVID B26 citations92
US8108610B1Jan 31, 2012
Cache-based control of atomic operations in conjunction with an external ALU block
GLASCO DAVID B31 citations92
US8862823B1Oct 14, 2014
Compression status caching
GLASCO DAVID B9 citations84
US8595437B1Nov 26, 2013
Compression status bit cache with deterministic isochronous latency
GLASCO DAVID B18 citations84
US8504773B1Aug 6, 2013
Storing dynamically sized buffers within a cache
GLASCO DAVID B17 citations84
US8060700B1Nov 15, 2011
System, method and frame buffer logic for evicting dirty data from a cache using counters and data types
GLASCO DAVID B18 citations84
US8949541B2Feb 3, 2015
Techniques for evicting dirty data from a cache using a notification sorter and count thresholds
GLASCO DAVID B6 citations73
US8874844B1Oct 28, 2014
Padding buffer requests to avoid reads of invalid data
GLASCO DAVID B5 citations73
US8627041B2Jan 7, 2014
Efficient line and page organization for compression status bit caching
GLASCO DAVID B5 citations73
US8156404B1Apr 10, 2012
L2 ECC implementation
GLASCO DAVID B4 citations63
US8099650B1Jan 17, 2012
L2 ECC implementation
GLASCO DAVID B2 citations63
US8539130B2Sep 17, 2013
Virtual channels for effective packet transfer
GLASCO DAVID B2 citations60
US8700862B2Apr 15, 2014
Compression status bit cache and backing store
GLASCO DAVID B1 citations52
ALTERA CORP
9 patentsUS7263624B2Aug 28, 2007
Methods and apparatus for power control in a scalable array of processor elements
ALTERA CORP48 citations96
US7836317B2Nov 16, 2010
Methods and apparatus for power control in a scalable array of processor elements
ALTERA CORP37 citations93
US7809932B1Oct 5, 2010
Methods and apparatus for adapting pipeline stage latency based on instruction type
ALTERA CORP23 citations93
US7340591B1Mar 4, 2008
Providing parallel operand functions using register file and extra path storage
ALTERA CORP20 citations84
US7386710B2Jun 10, 2008
Methods and apparatus for scalable array processor interrupt detection and response
ALTERA CORP4 citations74
US7266620B1Sep 4, 2007
System core for transferring data between an external device and memory
ALTERA CORP5 citations73
US7853779B2Dec 14, 2010
Methods and apparatus for scalable array processor interrupt detection and response
ALTERA CORP2 citations63
USRE41012ENov 24, 2009
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
ALTERA CORP4 citations63
US9009365B2Apr 14, 2015
System core for transferring data between an external device and memory
ALTERA CORP0 citations51
PTS CORP
6 patentsUS6845445B2Jan 18, 2005
Methods and apparatus for power control in a scalable array of processor elements
PTS CORP19 citations93
US6842811B2Jan 11, 2005
Methods and apparatus for scalable array processor interrupt detection and response
PTS CORP24 citations92
US6735690B1May 11, 2004
Specifying different type generalized event and action pair in a processor
PTS CORP25 citations92
US6965991B1Nov 15, 2005
Methods and apparatus for power control in a scalable array of processor elements
PTS CORP10 citations74
US6748517B1Jun 8, 2004
Constructing database representing manifold array architecture instruction set for use in support tool code creation
PTS CORP7 citations73
US7058790B2Jun 6, 2006
Cascaded event detection modules for generating combined events interrupt for processor action
PTS CORP4 citations63
BARRY EDWIN FRANKLIN
6 patentsUS8489858B2Jul 16, 2013
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN5 citations84
US9329866B2May 3, 2016
Methods and apparatus for adapting pipeline stage latency based on instruction type
BARRY EDWIN FRANKLIN2 citations63
US9158547B2Oct 13, 2015
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN1 citations63
US8413086B2Apr 2, 2013
Methods and apparatus for adapting pipeline stage latency based on instruction type
BARRY EDWIN FRANKLIN3 citations63
US8751772B2Jun 10, 2014
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN0 citations52
US8161267B2Apr 17, 2012
Methods and apparatus for scalable array processor interrupt detection and response
BARRY EDWIN FRANKLIN0 citations52
NVIDIA CORP
3 patentsPECHANEK GERALD GEORGE
3 patentsUS8296479B2Oct 23, 2012
System core for transferring data between an external device and memory
PECHANEK GERALD GEORGE1 citations62
US8117357B2Feb 14, 2012
System core for transferring data between an external device and memory
PECHANEK GERALD GEORGE1 citations62
US8397000B2Mar 12, 2013
System core for transferring data between an external device and memory
PECHANEK GERALD GEORGE0 citations51