Inventor

BOWERS BENJAMIN J

US17 patents

⚠️ This page may combine multiple inventors who share the name “BOWERS BENJAMIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOWERS BENJAMIN J

IBM

Systems and media to improve manufacturability of semiconductor devices

Methods, systems, and media to improve manufacturability of semiconductor devices

Top level hierarchy wiring via 1×N compiler

Creating integrated circuit capacitance from gate array structures

System for blocking multiple memory read port activation

CORREALE JR ANTHONY

Integrated design for manufacturing for 1×N VLSI design

Creating integrated circuit capacitance from gate array structures

Closed-loop 1×N VLSI design system

Creating integrated circuit capacitance from gate array structures

BOWERS BENJAMIN J

Compiler for closed-loop 1×N VLSI design

Methods, systems, and media to improve manufacturability of semiconductor devices

Compiler for closed-loop 1xN VLSI design

Compiler for closed-loop 1×N VLSI design

BAKER MATTHEW W

Uniquification and parent-child constructs for 1xN VLSI design

STEINMETZ PAUL M

Hierarchy reassembler for 1×N VLSI design

CYPRESS SEMICONDUCTOR CORP

Push/pull multiplexer bit

MENTOR GRAPHICS CORP

Compiler for closed-loop 1×N VLSI design