Inventor

MCGLONE ELIZABETH A

US45 patents

⚠️ This page may combine multiple inventors who share the name “MCGLONE ELIZABETH A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCGLONE ELIZABETH A

IBM

Implementing minimized latency and maximized reliability when data traverses multiple buses

System and method for managing mirrored memory transactions and error recovery

Scheduling of background scrub commands to reduce high workload memory request latency

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor with an expanded merge fetching queue

Operation of a multi-slice processor preventing early dependent instruction wakeup

Versatile lane configuration using a PCIe PIE-8 interface

Efficient scheduling of background scrub commands

Managing a divided load reorder queue

Peripheral component interconnect express (PCIe) ping in a switch-based environment

Peripheral component interconnect express (PCIe) ping in a switch-based environment

Broadcast for a distributed switch network

Operation of a multi-slice processor with an expanded merge fetching queue

Memory controller and method for copying mirrored memory that allows processor accesses to memory during a mirror copy operation

Memory controller and method for scrubbing memory without using explicit atomic operations

Managing mirrored memory transactions and error recovery

Method for implementing processor bus speculative data completion

Memory controller and method for scrubbing memory without using explicit atomic operations

Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch

Bandwidth limiting on generated PCIe packets from debug source

Implementing dynamic physical memory reallocation

Memory controller and method for multi-path address translation in non-uniform memory configurations

Memory controller granular read queue dynamic optimization of command selection

Flush avoidance in a load store unit

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Flexible and efficient configuration of multiple common interfaces

Compressed replay buffer

External settings that reconfigure the error handling behavior of a distributed PCIe switch

Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor

Accessing partial cachelines in a data cache

Operation of a multi-slice processor with dynamic canceling of partial loads

FREKING RONALD E

Versatile lane configuration using a PCIe PIe-8 interface

Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch

Bandwidth limiting on generated PCIE packets from debug source

Transmitting retry request associated with non-posted command via response credit channel

External settings that reconfigure the error handling behavior of a distributed PCIe switch

BLACKMON H LEE

Systems and methods to respond to error detection

System and method for responding to error detection

Managing memory refreshes

Systems and methods to efficiently schedule commands at a memory controller

BLACKMON HERMAN L

Memory controller for improved read port selection in a memory mirrored system

Memory controller for reducing time to initialize main memory

BARRETT WAYNE MELVIN

Apparatus for implementing processor bus speculative data completion