Inventor

CEROFOLINI GIANFRANCO

IT22 patents

⚠️ This page may combine multiple inventors who share the name “CEROFOLINI GIANFRANCO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CEROFOLINI GIANFRANCO

ST MICROELECTRONICS SRL

Nanometric structure and corresponding manufacturing method

Method for realizing a hosting structure of nanometric elements

Hosting structure of nanometric elements and corresponding manufacturing method

Process for cutting trenches in a single crystal substrate

Semiconductor integrated electronic device and corresponding manufacturing method

Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components

Method and device for demultiplexing a crossbar non-volatile memory

Semiconductor integrated electronic device and corresponding manufacturing method

Nanometric device with a hosting structure of nanometric elements

Electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components

Method for realizing a multispacer structure, use of said structure as a mold and circuital architectures obtained from said mold

Method and device for demultiplexing a crossbar non-volatile memory

Method for realizing a nanometric circuit architecture between standard electronic components and semiconductor device obtained with said method

Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components

ATES COMPONENTI ELETTRON

Process for making CMOS field-effect transistors

Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation

NARDUCCI DARIO

Seebeck/peltier thermoelectric conversion device having phonon confinement layers of crystalline semiconductor containing angstrom-sized organic groups as semiconductor atoms substituents within the crystal lattice and fabrication process

Seebeck/peltier thermoelectric conversion device employing treated films of semiconducting material not requiring nanometric definition

DONEGANI GUIDO IST

SOI structure with a deep thin oxide layer prepared by ION implantation at high energy followed by thermal treatment

SGS MICROELETTRONICA SPA

Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits

SGS THOMSON MICROELECTRONICS

Low dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic material

CONSORZIO DELTA TI RES

Seebeck/Peltier thermoelectric conversion element with parallel nanowires of conductor or semiconductor material organized in rows and columns through an insulating body and process