Inventor

HSU CHIA-LIN

TW62 patents

⚠️ This page may combine multiple inventors who share the name “HSU CHIA-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU CHIA-LIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Structure and method for metal gates with roughened barrier layer

Structure and method for metal gates with roughened barrier layer

Structure and method for metal gates with roughened barrier layer

Composite contact plug structure and method of making same

Electrostatic discharge circuit and method of operating same

Composite contact plug structure and method of making same

Composite contact plug structure and method of making same

Interconnect structure and method of forming the same

Power clamp

Semiconductor device and method for fabricating the same

Power clamp

Low-k dielectric damage prevention

Electrostatic discharge circuit and method of operating same

Low-k dielectric damage prevention

Semiconductor device and method for fabricating the same

Method for detecting environmental parameter in semiconductor fabrication facility

Method for detecting environmental parameter in semiconductor fabrication facility

Integrated circuit protection device and method

Composite contact plug structure and method of making same

Method for silicide formation

Method for silicide formation

UNITED MICROELECTRONICS CORP

Method of forming a dual damascene via by using a metal hard mask layer

Method for fabricating a high-density capacitor

Method of forming embedded capacitor structure applied to logic integrated circuit

Method for forming a semiconductor structure

Electroplating apparatus including a real-time feedback system

Method of fabricating semiconductor patterns

Multigate field effect transistor and process thereof

Control system for in-situ feeding back a polish profile

Method for planarization of wafers with high selectivities

Method for removing carbon-rich particles adhered on a copper surface

Planarization process for pre-damascene structure including metal hard mask

Chemical mechanical polishing process

Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same

Chemical mechanical polishing equipment

Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same

Chemical mechanical polishing method for copper

Manufacturing method for a shallow trench isolation

Manufacturing method of non-planar FET

LIAO CHIN-I

Multi-gate field-effect transistor and process thereof

Semiconductor process

Method for manufacturing multi-gate transistor device

HSU CHUN-WEI

Semiconductor device

Semiconductor device having metal gate and manufacturing method thereof

CHIEN CHIN-CHENG

Non-planar FET

Fabrication method for semiconductor devices

TAIWAN SEMICONDUCTOR MFG

Interconnect structure and method of forming the same

LIAO PO-JUI

Method of manufacturing semiconductor device having metal gates

HSU CHIA-LIN

Planarization process for pre-damascene structure including metal hard mask

TSAO WEI-CHE

Method for manufacturing through-silicon via