Inventor

CHAKRABORTY KANAD

US8 patents

⚠️ This page may combine multiple inventors who share the name “CHAKRABORTY KANAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LATTICE SEMICONDUCTOR CORP

4 patents

US9618579B2Apr 11, 2017

Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs

LATTICE SEMICONDUCTOR CORP10 citations82

US8977917B2Mar 10, 2015

Highly secure and extensive scan testing of integrated circuits

LATTICE SEMICONDUCTOR CORP3 citations69

US9728273B2Aug 8, 2017

Embedded memory testing using back-to-back write/read operations

LATTICE SEMICONDUCTOR CORP3 citations63

US9530486B1Dec 27, 2016

Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuits

LATTICE SEMICONDUCTOR CORP2 citations60

IBM

2 patents

US7047163B1May 16, 2006

Method and apparatus for applying fine-grained transforms during placement synthesis interaction

IBM25 citations89

US6532578B2Mar 11, 2003

Method of configuring integrated circuits using greedy algorithm for partitioning of N points in P isothetic rectangles

IBM9 citations73

AGERE SYSTEMS INC

2 patents

US7511535B2Mar 31, 2009

Fine-grained power management of synchronous and asynchronous datapath circuits

AGERE SYSTEMS INC15 citations80

US7409659B2Aug 5, 2008

System and method for suppressing crosstalk glitch in digital circuits

AGERE SYSTEMS INC13 citations78