Inventor

PARTHASARATHY VASUDEVAN

US28 patents

⚠️ This page may combine multiple inventors who share the name “PARTHASARATHY VASUDEVAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARTHASARATHY VASUDEVAN

BROADCOM CORP

High speed time-interleaved ADC gain offset and skew mitigation

Flexible ADC calibration technique using ADC capture memory

Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery

Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery

Method and system for testing devices using loop-back pseudo random data

Method and apparatus for reference-less repeater with digital control

Transceiver system and method having a transmit clock signal phase that is phase-locked with a receive clock signal phase

State based algorithm to minimize mean squared error

Generalized transmit pre-coding for optical and backplane channels

Systems for high-speed backplane applications using FEC encoding

Apparatus and method for automatic polarity swap in a communications system

Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase

System for monitoring the quality of a communications channel with mirror receivers

System and method of phase-locking a transmit clock signal phase with a receive clock signal phase

Method of monitoring the quality of a communications channel

System for monitoring the quality of a communications channel with mirror receivers

Apparatus and method for automatic polarity swap in a communications system

Systems for high-speed backplane applications using pre-coding

Multi-protocol communications receiver with shared analog front-end

BLISS WILLIAM

Systems for high-speed backplane applications using pre-coding

Systems for high-speed backplane applications using FEC encoding

AMIRICHIMEH ABBAS

Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase

Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase

THOMSON LICENSING SA

Truncated metric for NTSC interference rejection in the ATSC-HDTV trellis decoder

THOMSON LICENSING

Code mapping in a trellis decoder

WANG JOHN

On-chip interferers for standards compliant jitter tolerance testing

TELANG VIVEK

Multi-protocol communications receiver with shared analog front-end

AVAGO TECH INT SALES PTE LID

Soft information generation for concatenated forward error correction in digiral signal processing