Inventor
MAGNUS ALAN J
US24 patents
⚠️ This page may combine multiple inventors who share the name “MAGNUS ALAN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
8 patentsUS7132303B2Nov 7, 2006
Stacked semiconductor device assembly and method for forming
FREESCALE SEMICONDUCTOR INC7 citations72
US9070669B2Jun 30, 2015
Wettable lead ends on a flat-pack no-lead microelectronic package
FREESCALE SEMICONDUCTOR INC6 citations70
US9455216B2Sep 27, 2016
Semiconductor device package and method of manufacture
FREESCALE SEMICONDUCTOR INC2 citations62
US9346671B2May 24, 2016
Shielding MEMS structures during wafer dicing
FREESCALE SEMICONDUCTOR INC2 citations62
US7892950B2Feb 22, 2011
Methodology for processing a panel during semiconductor device fabrication
FREESCALE SEMICONDUCTOR INC2 citations61
US9691743B2Jun 27, 2017
Localized redistribution layer structure for embedded component package and method
FREESCALE SEMICONDUCTOR INC1 citations51
US9093436B2Jul 28, 2015
Semiconductor device package and method of manufacture
FREESCALE SEMICONDUCTOR INC0 citations51
US9458012B2Oct 4, 2016
Method for shielding MEMS structures during front side wafer dicing
FREESCALE SEMICONDUCTOR INC0 citations41
MAGNUS ALAN J
4 patentsUS8822268B1Sep 2, 2014
Redistributed chip packages containing multiple components and methods for the fabrication thereof
MAGNUS ALAN J32 citations93
US9401338B2Jul 26, 2016
Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
MAGNUS ALAN J42 citations87
US8685790B2Apr 1, 2014
Semiconductor device package having backside contact and method for manufacturing
MAGNUS ALAN J5 citations67
US9281293B2Mar 8, 2016
Microelectronic packages having layered interconnect structures and methods for the manufacture thereof
MAGNUS ALAN J0 citations39
NXP USA INC
4 patentsUS10340251B2Jul 2, 2019
Method for making an electronic component package
NXP USA INC3 citations69
US10998231B2May 4, 2021
Method for increasing semiconductor device wafer strength
NXP USA INC1 citations56
US11450616B2Sep 20, 2022
Using a backside mask layer for forming a unique die mark identifier pattern
NXP USA INC1 citations53
US10056360B2Aug 21, 2018
Localized redistribution layer structure for embedded component package and method
NXP USA INC0 citations51
YAP WENG F
3 patentsUS9281286B1Mar 8, 2016
Microelectronic packages having texturized solder pads and methods for the fabrication thereof
YAP WENG F7 citations83
US9997492B2Jun 12, 2018
Optically-masked microelectronic packages and methods for the fabrication thereof
YAP WENG F2 citations73
US9401339B2Jul 26, 2016
Wafer level packages having non-wettable solder collars and methods for the fabrication thereof
YAP WENG F3 citations72