Inventor

ZHU HUILONG

US552 patents

⚠️ This page may combine multiple inventors who share the name “ZHU HUILONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHU HUILONG

IBM

Structure and method for fabricating self-aligned metal contacts

MOSFET with super-steep retrograded island

High performance MOSFET

High mobility CMOS circuits

Strained silicon NMOS devices with embedded source/drain

Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure

Test structures and method of defect detection using voltage contrast inspection

Structure and method for manufacturing strained FINFET

Dual gate FinFet

Channel MOSFET with strained silicon channel on strained SiGe

Method and manufacture of thin silicon on insulator (SOI) with recessed channel

Triple gate and double gate finFETs with different vertical dimension fins

finFET structure with multiply stressed gate electrode

Method of fabricating a field effect transistor having improved junctions

Structure and method of manufacturing a finFET device having stacked fins

Method of manufacturing a body-contacted finfet

Structure and method of fabricating FinFET with buried channel

Thermoelectric 3D cooling

Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom

Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure

FinFET SRAM with asymmetric gate and method of manufacture thereof

Nanoelectromechanical digital inverter

MOSFETs comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same

Structure and method of making double-gated self-aligned finFET having gates of different lengths

Structure and method of fabricating FINFET with buried channel

Structure and method for manufacturing strained FINFET

Method and structure for forming self-aligned, dual stress liner for CMOS devices

Dual stressed SOI substrates

Methods for manufacturing a finFET using a conventional wafer and apparatus manufactured therefrom

Strained Si on multiple materials for bulk or SOI substrates

Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film

Method and apparatus to increase strain effect in a transistor channel

Dual function FinFET, finmemory and method of manufacture

Thin channel FET with recessed source/drains and extensions

Structure and method for silicided metal gate transistors

Strained HOT (hybrid orientation technology) MOSFETs

Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels

Structure and method for manufacturing MOSFET with super-steep retrograded island

Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification

Structure for strained channel field effect transistor pair having a member and a contact via

ZHU HUILONG

Semiconductor device and method for manufacturing the same

Two-sided semiconductor structure

Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same

Field effect transistor having an asymmetric gate electrode

Triple gate and double gate finFETs with different vertical dimension fins

FAROOQ MUKTA G

Bonded structure employing metal semiconductor alloy bonding

Method of making 3D integrated circuits

YIN HAIZHOU

Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor

CHARTERED SEMICONDUCTOR MFG

Method of fabricating a transistor structure

ADVANCED MICRO DEVICES INC

Undercut and residual spacer prevention for dual stressed layers