Inventor

FOLTIN MARTIN

US38 patents

⚠️ This page may combine multiple inventors who share the name “FOLTIN MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FOLTIN MARTIN

HEWLETT PACKARD ENTPR DEV LP

Tunable and dynamically adjustable error correction for memristor crossbars

Circuits having selector devices with different I-V responses

Acceleration of model/weight programming in memristor crossbar arrays

Methods and systems for highly optimized memristor write process

Iterative write sequence interrupt

Self-healing dot-product engine

Re-encoding data associated with failed memory devices

Reference column sensing for resistive memory

Security and anomaly detection for Internet-of-Things devices

Memristance feedback tuning

Scalable microservices-driven industrial IoT controller architecture

Acceleration of model/weight programming in memristor crossbar arrays

Resistive and digital processing cores

Resistive and digital processing cores

Self-healing dot-product engine

Vertical JFET device for memristor array interface

Adjusting memory parameters

Data sensing in crosspoint memory structures

Detection of error patterns in memory dies

Multi-die dot-product engine to provision large scale machine learning inference applications

Error correction code in memory

Adjustable precision for multi-stage compute processes

Determining significance levels of error values in processes that include multiple layers

Managing data using a number of non-volatile memory arrays

Managing a multi-lane serial link

Non-volatile memory with multiple latency tiers

Sensing circuit for resistive memory

Method to track and clone data artifacts associated with distributed data processing pipelines

Data-aware storage tiering and lifetime data valuation for deep learning

Memristor memory with volatile and non-volatile states

System and method for processing convolutions on crossbar-based neural network accelerators for increased inference throughput

Resistive ratio-based memory cell

HEWLETT PACKARD DEVELOPMENT CO

Enabling verification of a minimal level sensitive timing abstraction model

Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction model

Load sensitivity modeling in a minimal level sensitive timing abstraction model

Minimal level sensitive timing abstraction model capable of being used in general static timing analysis tools

Minimal level sensitive timing representative of a circuit path

Link training for a serdes link