Inventor

HOPPER PETER J

US234 patents

⚠️ This page may combine multiple inventors who share the name “HOPPER PETER J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOPPER PETER J

NAT SEMICONDUCTOR CORP

Laser powered clock circuit with a substantially reduced clock skew

MEMS microphone

Integrated switching voltage regulator using copper process technology

MEMS inductor with very low resistance

Semiconductor device combining a MOSFET structure and a vertical-channel trench-substrate field effect device

High voltage ESD LDMOS-SCR with gate reference voltage

On-chip power inductor

Dual direction ESD clamp based on snapback NMOS cell with embedded SCR

Apparatus and method for precision trimming of integrated circuits using anti-fuse bond pads

BJT with ESD self protection

Substrate independent multiple input bi-directional ESD protection structure

Snapback clamp having low triggering voltage for ESD protection

High voltage tolerant electrostatic discharge (ESD) protection clamp circuitry

Method of forming through-the-wafer metal interconnect structures

Programming method for nonvolatile memory cell

Method of etching a lateral trench under an extrinsic base and improved bipolar transistor

Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of control gate voltage

Non-volatile memory cell with gated diode and MOS transistor and method for using such cell

Electrostatic discharge (ESD) protection circuit

Split-gate flash memory cell with a tip in the middle of the floating gate

LVTSCR with a holding voltage that is greater than a DC bias voltage on a to-be-protected node

MOSFET-based electrostatic discharge (ESD) protection structure with a floating heat sink

Process for forming physical gate length dependent implanted regions using dual polysilicon spacers

Integrated circuits with inductors

Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits

Patterned magnetic layer on-chip inductor

Apparatus and method for forming heat sinks on silicon on insulator wafers

Complementary vertical SCRs for SOI and triple well processes

Spin-injection devices on silicon material for conventional BiCMOS technology

Spin-polarization of carriers in semiconductor materials for spin-based microelectronic devices

Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection

Memory cell with a capacitive structure as a control gate and method of forming the memory cell

Direct implantation of fluorine into the channel region of a PMOS device

Bi-directional ESD protection structure for BiCMOS technology

High holding voltage ESD protection structure for BiCMOS technology

MEMS pressure sensing device

DC-DC voltage converter with reduced output voltage ripple

Semiconductor structure with galvanically-isolated signal and power paths

TEXAS INSTRUMENTS INC

Vapor cell structure having cavities connected by channels for micro-fabricated atomic clocks, magnetometers, and other devices

Multiple-cavity vapor cell structure for micro-fabricated atomic clocks, magnetometers, and other devices

Vapor cell structure having cavities connected by channels for micro-fabricated atomic clocks, magnetometers, and other devices

Multiple-cavity vapor cell structure for micro-fabricated atomic clocks, magnetometers, and other devices

Atomic clocks and magnetometers with vapor cells having condensation sites in fluid communication with a cavity to hold a vapor condensation away from an optical path

FOVEON INC

Imager with improved sensitivity

Method of forming a bandgap tuned vertical color imager cell

EASTMAN KODAK CO

Low-cost method of forming a color imager

Active pixel sensor cell with integrating varactor and method for using such cell

FRENCH WILLIAM

Micro-fabricated atomic magnetometer and method of forming the magnetometer

HOPPER PETER J

Semiconductor capacitor with large area plates and a small footprint that is formed with shadow masks and only two lithography steps

VASHCHENKO VLADISLAV

EDS protection diode with pwell-nwell resurf