Inventor

FIFIELD JOHN A

US166 patents

⚠️ This page may combine multiple inventors who share the name “FIFIELD JOHN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FIFIELD JOHN A

IBM

Crosstalk-shielded-bit-line dram

High impedance antifuse

Programmable latch device with integrated programmable element

Methods and apparatus for blowing and sensing antifuses

Impedance control using fuses

Self biased differential amplifier with hysteresis

On-chip thermometry for control of chip operating temperature

Integrated fuse latch and shift register for efficient programming and fuse readout

Dynamic ram with on-chip ecc and optimized bit and word redundancy

Antifuse latch device with controlled current programming and variable trip point

High frequency valid data strobe

Multi-level storage gain cell with stepline

Interlocked on-chip ECC system

Programmable delay element and synchronous DRAM using the same

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature

Adjustable reference voltage generator for single-ended DRAM sensing devices

On-chip ECC status

Structure for power-efficient cache memory

Stress control mechanism for use in high-voltage applications in an integrated circuit

Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable

Changing chip function based on fuse states

Changing chip function based on fuse states

ECC based system and method for repairing failed memory elements

Voltage divider for integrated circuits

Fuse latch with compensated programmable resistive trip point

Temperature programmable timing delay system

Redundant antifuse segments for improved programming efficiency

Constant impedance driver for high speed interface

Automatic off-chip driver adjustment based on load characteristics

Control of hysteresis characteristic within a CMOS differential receiver

Method and apparatus for protecting off chip driver circuitry employing a split rail power supply

Gain memory cell with diode

Apparatus for reducing soft errors in dynamic circuits

Stabilized direct sensing memory architecture

Impedance control using fuses

Fast check bit write for a semiconductor memory

Memory system reset circuit

Dual level error detection and correction employing data subsets from previously corrected data

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

Leakage compensation circuit

Programmable delay element and synchronous DRAM using the same

OLDCASTLE INC

Composite building element and methods of making and using the same

Lightweight concrete roof tiles and similar products

Roof tile

Roof tiles

Roof tiles

GLOBALFOUNDRIES INC

Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing

Voltage-aware adaptive static random access memory (SRAM) write assist circuit

OLDCASTLE PRECAST INC

Insulative building panel with transverse fiber reinforcement