Inventor

MEHTA SUNIL

US47 patents

⚠️ This page may combine multiple inventors who share the name “MEHTA SUNIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEHTA SUNIL

ADVANCED MICRO DEVICES INC

CMOS EEPROM cell with tunneling window in the read path

Isolation using self-aligned trench formation and conventional LOCOS

Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device

Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate

Method of forming multiple gate oxide thicknesses on a wafer substrate

Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer

Field implant for semiconductor device

Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration

Borderless vias

High density multi-level metallization and interconnection structure

Manufacturing process for borderless vias with respect to underlying metal

Borderless vias

Method for annealing damaged semiconductor regions allowing for enhanced oxide growth

Field implant for semiconductor device

Field leakage by using a thin layer of nitride deposited by chemical vapor deposition

Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array

Method and system for providing electrical insulation for local interconnect in a logic circuit

Method of charging and discharging floating gage transistors to reduce leakage current

Method and system for providing electrical insulation for local interconnect in a logic circuit

LATTICE SEMICONDUCTOR CORP

Zero-power programmable memory cell

Non-volatile memory cell with enhanced cell drive current

Formation of high voltage transistor with high breakdown voltage

Zero-power logic cell for use in programmable logic devices

Shallow trench isolation (STI) with trench liner of increased thickness

Zero power memory cell with improved data retention

Circuit layout for improved performance while preserving or improving density

Zero power memory cell with reduced threshold voltage

Shallow trench isolation (STI) with trench liner of increased thickness

MEHTA SUNIL

Apparatus for manipulating particles using at least one chamber having an inlet and an opposed outlet

Methods and systems for manipulating particles using a fluidized bed

Methods and systems for manipulating particles using a fluidized bed

Identifying and ranking networked biographies and referral paths corresponding to selected qualifications

HENRY JACKSON FOUNDATION FOR T

Method of dynamic retardation of cell cycle kinetics to potentiate cell damage

Method of dynamic retardation of cell cycle kinetics to potentiate cell damage

ANTIGENICS INC

Heat shock protein-based vaccines and immunotherapies

Heat shock protein-based vaccines and immunotherapies

SARTORIUS STEDIM NORTH AMERICA INC

Methods and systems for manipulating particles using a fluidized bed

Methods, systems and apparatus for manipulating particles

NIMBLECAT INC

Social-mobile-local (SML) networking with intelligent semantic processing

Identifying and ranking networked biographies and referral paths corresponding to selected qualifications

MEASURE PROTOCOL LTD

Device-side validation of screen recordings

Generating structured data from screen recordings

VANTIS CORP

Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration

DHINGRA ANURAG

High availability network processing system

APPLE INC

Activity-driven capacitance reduction to reduce dynamic power consumption in an integrated circuit

INFILCO DEGREMONT INC

Biological-chemical treatment of liquid organic wastewater

HIGHWIRE PRESS INC

Rejected article tracker