P

Inventor

KAUL HIMANSHU

US43 patents
⚠️ This page may combine multiple inventors who share the name “KAUL HIMANSHU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

36 patents
US11360767B2Jun 14, 2022

Instructions and logic to perform floating point and integer operations for machine learning

INTEL CORP39 citations98
US11169799B2Nov 9, 2021

Instructions and logic to perform floating-point and integer operations for machine learning

INTEL CORP36 citations98
US11080046B2Aug 3, 2021

Instructions and logic to perform floating point and integer operations for machine learning

INTEL CORP38 citations98
US10474458B2Nov 12, 2019

Instructions and logic to perform floating-point and integer operations for machine learning

INTEL CORP46 citations98
US10353706B2Jul 16, 2019

Instructions and logic to perform floating-point and integer operations for machine learning

INTEL CORP47 citations98
US9104474B2Aug 11, 2015

Variable precision floating point multiply-add circuit

INTEL CORP75 citations95
US7154300B2Dec 26, 2006

Encoder and decoder circuits for dynamic bus

INTEL CORP19 citations92
US9680765B2Jun 13, 2017

Spatially divided circuit-switched channels for a network-on-chip

INTEL CORP9 citations84
US9652425B2May 16, 2017

Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)

INTEL CORP13 citations84
US7519646B2Apr 14, 2009

Reconfigurable SIMD vector processing system

INTEL CORP13 citations84
US9979668B2May 22, 2018

Combined guaranteed throughput and best effort network-on-chip

INTEL CORP7 citations81
US12141578B2Nov 12, 2024

Instructions and logic to perform floating point and integer operations for machine learning

INTEL CORP2 citations73
US10599429B2Mar 24, 2020

Variable format, variable sparsity matrix multiplication instruction

INTEL CORP4 citations73
US9866476B2Jan 9, 2018

Parallel direction decode circuits for network-on-chip

INTEL CORP3 citations73
US9843441B2Dec 12, 2017

Compact, low power advanced encryption standard circuit

INTEL CORP4 citations73
US9787571B2Oct 10, 2017

Link delay based routing apparatus for a network-on-chip

INTEL CORP3 citations73
US9626334B2Apr 18, 2017

Systems, apparatuses, and methods for K nearest neighbor search

INTEL CORP3 citations73
US10642614B2May 5, 2020

Reconfigurable multi-precision integer dot-product hardware accelerator for machine-learning applications

INTEL CORP3 citations70
US12217053B2Feb 4, 2025

Instructions and logic to perform floating point and integer operations for machine learning

INTEL CORP0 citations63
US12039331B2Jul 16, 2024

Instructions and logic to perform floating point and integer operations for machine learning

INTEL CORP0 citations63
US11720355B2Aug 8, 2023

Instructions and logic to perform floating point and integer operations for machine learning

INTEL CORP0 citations63
US11868296B2Jan 9, 2024

High bandwidth core to network-on-chip interface

INTEL CORP0 citations62
US11321263B2May 3, 2022

High bandwidth core to network-on-chip interface

INTEL CORP0 citations62
US10944402B1Mar 9, 2021

Reconfigurable interconnect structure in integrated circuits

INTEL CORP1 citations60
US11288040B2Mar 29, 2022

Floating-point dot-product hardware with wide multiply-adder tree for machine learning accelerators

INTEL CORP0 citations52
US10440377B2Oct 8, 2019

Motion estimation for video processing

INTEL CORP0 citations52
US9992042B2Jun 5, 2018

Pipelined hybrid packet/circuit-switched network-on-chip

INTEL CORP1 citations52
US9940236B2Apr 10, 2018

Pointer chasing across distributed memory

INTEL CORP0 citations52
US9923730B2Mar 20, 2018

System for multicast and reduction communications on a network-on-chip

INTEL CORP0 citations52
US9680459B2Jun 13, 2017

Edge-aware synchronization of a data signal

INTEL CORP0 citations52
US9577634B2Feb 21, 2017

Scalable crossbar apparatus and method for arranging crossbar circuits

INTEL CORP0 citations52
US7913101B2Mar 22, 2011

Method and apparatus for treating a signal

INTEL CORP0 citations52
US12334392B2Jun 17, 2025

Multi-height interconnect trenches for resistance and capacitance optimization

INTEL CORP0 citations50
US10374793B2Aug 6, 2019

Simon-based hashing for fuse validation

INTEL CORP0 citations50
US9961019B2May 1, 2018

Adaptively switched network-on-chip

INTEL CORP1 citations50
US10303735B2May 28, 2019

Systems, apparatuses, and methods for K nearest neighbor search

INTEL CORP0 citations42

ANDERS MARK

2 patents

UNIV MICHIGAN

2 patents

SATPATHY SUDHIR

1 patent

ANDERS MARK A

1 patent

MATHEW SANU K

1 patent